Denon AV SURROUND RECEIVER AVR-5308CI, Service Manual

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78
AVR-5308CI / AVC-A1HD
M30627FHPGP Terminal Function
Pin Pin Name Symbol I/O Type
Det
Op(Int.) Op(Ext.) Res Function
1 VREF VREF - -
-
- - - AD ref. +3.3V
2 AVCC AVCC - -
-
- - - AD +3.3V
3 P97/SIN4 DSPMISO I -
Lv
- Eu Z DSP control pin(ADSP-21366)/(ADSP-21367)
4 P96/SOUT4 DSPMOSI O C
-
- Eu Z DSP control pin(ADSP-21366)/(ADSP-21367)
5 P95/CLK4 DSPICLK O C
-
- Eu Z DSP control pin(ADSP-21366)/(ADSP-21367)
6 P94 DIRCE5 O C
-
- - Z DIR selector control pin(LC89057W-VF4A)
7 P93 DIRCE1 O C
-
- - Z DIR selector control pin(LC89057W-VF4A)
8 P92/SOUT3 DIRDIN O C
-
- - Z DIR selector control pin(LC89057W-VF4A)
9 P91/SIN3 DIRDOUT I -
Lv
- Eu Z DIR selector control pin(LC89057W-VF4A)
10 P90/CLK3 DIRCLK O C
-
- - Z DIR selector control pin(LC89057W-VF4A)
11 P141 (DSP5 FLAG0) O -
Lv
- - Z Not used(DSP5 control pin(ADSP-21367))
12 P140 (SUP ACK) O C
-
- Ed Z Not used
13 BYTE BYTE - -
-
- - - GND (Ext. data bus bit width switching, 16bit : L)
14 CNVCS CNVSS - -
-
- Ed -
Single-chip / Micro-processor mode switching (Normal single-chip : L,Rewrite boot
program start : H input set)
15 P87 Z1 VERST O C
-
- Eu Z ZONE1 Video encoder reset(ADV7320)
16 P86 Z1 VDRST O C
-
- Eu Z Video decoder reset(ADV7430)
17 RESET SUBRESET I -
Lv
- Eu L Reset input
18 XOUT X1 O -
-
- - - Oscillator connection
19 VSS VSS - -
-
- - - GND
20 XIN X2 I -
-
- - - Oscillator connection
21 VCC VCC - -
-
- - - +3.3V
22 P85/NMI _NMI I -
-
- - - Not used (Fixed to H)
23 P84/INT2 CEC_IN I -
E ↓ &L
- Eu Z CEC-D signal input pin(SII9185)
24 P83/INT1 ACKSIMO I -
E ↓ &L
- Ed Z
MAIN-SUB
μ
com comm. Control input pin
25 P82/INT0 SUBBDOWN I -
E ↓ &L
Eu Z Power down detect (Power down : L)
26 P81 IP RST O C
-
- Ed Z IP CONV(FLI2310) reset
27 P80 GUI WRITE O -
-
- - Z GUI ROM rewrite control(ACTIVE"L")
28 P77 SUBTDO I -
-
- Ed Z PLD rewrite control(JTAG)
29 P76 MPLD CS MAIN/SUBTMS O C
-
- - Z MAIN FPGA(PLD) control pin/PLD rewrite control(JTAG)
30 P75 MPLD DATA/SUBTDI O C
-
- - Z MAIN FPGA(PLD) control pin/PLD rewrite control(JTAG)
31 P74 MPLD CLK/SUBTCK O C
-
- - Z MAIN FPGA(PLD) control pin/PLD rewrite control(JTAG)
32 P73/CTS2 VIDEO POWER O C
-
- Ed Z VIDEO POWER control output (H : ON)
33 P72/CLK2 DIGITAL POWER O C
-
- Ed Z DIGITAL POWER control output (H : ON)
34 P71/RXD2 VSCL I/O C
-
- Eu Z
VIDEO I2C- IP CONV(FLI2310)/V_ENCODER(ADV7320)/V_DECODER(ADV7430)/
GUI_FPGA control pin
35 P70/TXD2 VSDA I/O C
-
- Eu Z
VIDEO I2C- IP CONV(FLI2310)/V_ENCODER(ADV7320)/V_DECODER(ADV7431)/
GUI_FPGA control pin
36 P67/TXD1
TXD/(SUP TxD
)/REALTA_RX SO
O C
-
- Eu Z Data transmission output to outside/REALTA rewrite control pin
37 VCC1 VCC1 - -
-
- - Z +3.3V
38 P66/RXD1
RXD/(SUP Rxd)
/REALTA_TX SI
I -
Lv
- Eu Z Data receive input from outside/REALTA rewrite control pin
39 VSS VSS - -
-
- - Z GND
40 P65/CLK1 (SUP CLK) O C
-
- Eu Z Not used
41 P64/CTS1 CEC_OUT O C
-
- Eu Z CEC-D signal output pin(SII9185)
42 P63/TXD0 SOMI O C
-
- - Z
MAIN-SUB
μ
com comm. control pin
43 P62/RXD0 SIMO I -
-
- - Z MAIN-SUB
μ
com comm. control pin
44 P61/CLK0 CLKSIMO I -
-
- - Z
MAIN-SUB
μ
com comm. control pin
45 P60/CTS0 REQSOMI O C
-
- - Z
MAIN-SUB
μ
com comm. control pin
46 P137 (DSP6 FLAG0) O -
Lv
- - Z Not used(DSP6 control pin(ADSP-21367))
47 P136 ADOVER I -
-
- Eu Z A/D OVERLOAD detect
48 P135 (Z2 VERST) O C
-
- Eu Z (ZONE2 Video encoder reset(ADV7320) for AVPA1HD)
49 P134 (Z2 VDRST) O C
-
- Eu Z (Video decoder reset(ADV7430) for AVPA1HD)
50 P57 (DSP5 RST) O C
-
- - Z Not used(DSP5(ADSP-21367)reset output pin(reset : L))
51 P56 Z1 CFSEL0 O C
-
- Ed Z ENCODER output set (480i/576i,480p/576p : H)
52 P55/EPM
(DSP6 RST)
/(FRASHEPM)
O C
-
- Ed Z Not used(DSP6(ADSP-21367)reset output pin(reset : L))/(Rewrite boot : L input)
53 P54 VSEL CLK O C
-
- - Z GUI built-in VIDEO SW control pin
54 P133 DEXPCLK O C
-
- - Z Output pin for DIGITAL expander control (TC4094BF)