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Register Description
71
0xB000C010
User Pulse Register 0
W
0xB000C014
User Pulse Register 1
W
0xB000C018
User Pulse Register 2
W
0xB000C01C
Reserved
–
0xB000C020
User Control 0
W
0xB000C024
User Control 1
W
0xB000C028
User Control 2
W
0xB000C02C
Reserved
–
0xB000C030
Counter Timer Status
R
0xB0010000
Digital Port 0 INT Mask Register
(Right Justified Data)
R/W
0xB0010004
Digital Data Port 0 (Right Justified Data)
R/W
0xB0010008
Digital Data Port 1 (Right Justified Data)
R/W
0xB001000C
Digital Data Port 2 (Right Justified Data)
R/W
0xB0014000
SB Control & Address Register
–
CE3
R/W
0xA0000000
16-Bit SB Data Register
–
CE2 (20 ns; set up for 2 cycles)
W
0xA0000004
16-Bit SB Data Register
–
CE2 (20 ns; ECLKIN/2)
R
a. Refer to the
DT9840 Series DSP Library User’s Manual
for more information on the CDB file.
b. For the DT9841-VIB module, bit 0 of digital port 2 is used as the SCL clock, and bit 1 of digital port 2 is
used as the SDA data output; the remaining bits (2-7) of digital port 2 are reserved. See
for more
information.
c. This register contains eight debug LEDs that are right-hand justified. Debug LEDs are not supported on
the DT9841E. Bits 0 (D0) through 7 (D7) correspond to LEDs CR5 through CR12. (The LEDs were
numbered differently on some early modules.)
If an error is detected in a running DT9840 Series DSP program, these LEDs turn on.
Table 15: Memory Space Address Map (cont.)
Address
Register Description
Type
Summary of Contents for DT9840 Series
Page 1: ...DT9840 Series UM 19197 T User s Manual Title Page ...
Page 4: ......
Page 44: ...Chapter 1 44 ...
Page 76: ...Chapter 2 76 ...
Page 98: ...Appendix A 98 ...
Page 124: ...Appendix B 124 ...