Data Translation DT9834 Series, User Manual

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Chapter 5
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• Analog threshold trigger – An analog threshold trigger event occurs when the signal on
the first channel in the analog input channel list rises above (low-to-high transition) a
programmable threshold level. Using software, specify the trigger source as a positive
threshold trigger.
You can use any one of the 16 analog input channels as the analog trigger. The analog
trigger channel must be the first entry in the analog input channel list.
You specify the threshold level by setting the value of D/A subsystem 1. Specify a value
between 0 and 255, where 0 equals 0 V and 255 10 V.
Data Format and Transfer
DT9834 Series modules use offset binary data encoding, such as 000 (for 12-bit modules) or
0000 (for 16-bit modules) to represent negative full-scale, and FFFh (for 12-bit modules) or
FFFFh (for 16-bit modules) to represent positive full-scale. Use software to specify the data
encoding as binary.
The ADC outputs FFFh (for 12-bit modules) or FFFFh (for 16-bit modules) for above-range
signals, and 000 (for 12-bit modules) or 0000 (for 16-bit modules) for below-range signals.
Before you begin acquiring data, you must allocate buffers to hold the data. An event is
returned whenever a buffer is filled. This allows you to move and/or process the data as
needed.
We recommend that you allocate a minimum of two buffers for analog input operations. Data
is written to multiple allocated input buffers continuously; when no more empty buffers are
available, the operation stops. The data is gap-free.
Error Conditions
The DT9834 Series modules can report an error if one of the following conditions occurs:
• A/D Over Sample – The A/D sample clock rate is too fast. This error is reported if a new
A/D sample clock pulse occurs while the ADC is busy performing a conversion from the
previous A/D sample clock pulse. The host computer can clear this error. To avoid this
error, use a slower sampling rate.
• Input FIFO Overflow – The analog input data is not being transferred fast enough to the
host computer. The host computer can clear this error, but the error will continue to be
generated if the Input FIFO is still full. To avoid this error, close other applications that
may be running while you are acquiring data. If this has no effect, try using a computer
with a faster processor or reduce the sampling rate.
If one of these error conditions occurs, the module stops acquiring and transferring data to the
host computer.