Chapter 4
Signal Connections
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National Instruments Corporation
4-31
PCI-MIO E Series User Manual
TRIG2 Signal
Any PFI pin can externally input the TRIG2 signal, which is available
as an output on the PFI1/TRIG2 pin.
Refer to Figure 4-12 for the relationship of TRIG2 to the DAQ
sequence.
As an input, the TRIG2 signal is configured in the edge-detection mode.
You can select any PFI pin as the source for TRIG2 and configure the
polarity selection for either rising or falling edge. The selected edge of
the TRIG2 signal initiates the posttriggered phase of a pretriggered
acquisition sequence. In pretriggered mode, the TRIG1 signal initiates
the data acquisition. The scan counter indicates the minimum number of
scans before TRIG2 can be recognized. After the scan counter
decrements to zero, it is loaded with the number of posttrigger scans to
acquire while the acquisition continues. The board ignores the TRIG2
signal if it is asserted prior to the scan counter decrementing to zero.
After the selected edge of TRIG2 is received, the board will acquire a
fixed number of scans and the acquisition will stop. This mode acquires
data both before and after receiving TRIG2.
As an output, the TRIG2 signal reflects the posttrigger in a pretriggered
acquisition sequence. This is true even if the acquisition is being
externally triggered by another PFI. The TRIG2 signal is not used in
posttriggered data acquisition. The output is an active high pulse with a
pulse width of 50 to 100 ns. This output is set to tri-state at startup.
Figures 4-17 and 4-18 show the input and output timing requirements
for the TRIG2 signal.
Figure 4-17. TRIG2 Input Signal Timing
Rising-edge
polarity
Falling-edge
polarity
tw
tw = 10 ns minimum
