DS1820
021497 18/27
READ/WRITE TIMING DIAGRAM Figure 12
1–WIRE
BUS
MASTER WRITE “0” SLOT
MASTER WRITE “1” SLOT
60
µ
s<T
X
“0”<120
µ
s
>1
µ
s
15
µ
s
3
0 µ
s
15
µ
s
3
0 µ
s
DS1820 SAMPLES
MIN
TYP
MAX
MASTER READ “0” SLOT
MASTER READ “1” SLOT
15
µ
s
>1
µ
s
MASTER SAMPLES
15
µ
s
15
µ
s
DS1820 SAMPLES
MIN
TYP
MAX
1
µ
s< t
REC
<
∞
1
µ
s< t
REC
<
∞
15
µ
s
3
0 µ
s
15
µ
s
MASTER SAMPLES
LINE TYPE LEGEND:
Bus master active low
Both bus master and
DS1820 active low
DS1820 active low
Resistor pull–up
V
CC
GND
ÇÇÇ
ÇÇÇ
ÇÇÇ
1–WIRE
BUS
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
V
CC
GND
ÇÇÇ
ÇÇÇ
ÇÇÇ
