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DS3112

91 of 133

Bit

#

Register Name:

THDLC

Register Description:

Transmit HDLC FIFO

Register Address:

84h

7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0
Default

0 0 0 0 0 0 0 0

Bit

# 15 14 13 12 11 10 9 8

Name — — — — — — —

TMEND

Default

— — — — — — — 0

Note 1: When the CPU bus is operated in the 8-bit mode (CMS = 1), the host should always write to the lower byte (bits 0 to 7) first followed
by the upper byte (bits 8 to 15).
Note 2: The THDLC is a write-only register.
Note 3: The Transmit FIFO can be filled to a maximum capacity of 256 bytes. When the Transmit FIFO is full, it will not accept any
additional data.

Bits 0 to 7: Transmit FIFO Data (D0 to D7).

Data for the Transmit FIFO can be written to these bits. D0 is the

LSB and is transmitted first while D7 is the MSB and is transmitted last.

Bit 8: Transmit Message End (TMEND).

This bit is used to delineate multiple messages in the Transmit FIFO. It

should be set to a one when the last byte of a packet is written to the Transmit FIFO. The setting of this bit
indicates to the HDLC controller that the message is complete and that it should calculate and add in the CRC
checksum and at least two flags. This bit should be set to zero for all other data written to the FIFO. All HDLC
messages must be at least 2 bytes in length.

9.3 HDLC Status and Interrupt Register Description

Register Name:

HSR

Register Description:

HDLC Status Register

Register Address:

86h

Bit

# 7 6 5 4 3 2 1 0

Name

TUDR

RPE

RPS

RHWM

—

TLWM

—

TEND

Default — — — — — — — —

Bit

# 15 14 13 12 11 10 9 8

Name

RABT

REMPTY

ROVR

TEMPTY TFL3 TFL2

TFL1

TFL0

Default — — — — — — — —

Note: See

for details on the signal flow for the status bits in the HSR register. Bits that are underlined are read-only; all other

bits are read-write.

Bit 0: Transmit Packet End (TEND).

This latched read-only event-status bit will be set to a one each time the

transmit HDLC controller reads a transmit FIFO byte with the corresponding TMEND bit set or if a FIFO underrun
occurs. This bit will be cleared when read and will not be set again until another message end is detected. The
setting of this bit can cause a hardware interrupt to occur if the TEND bit in the Interrupt Mask for HSR (IHSR)
register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read.

Bit 2: Transmit FIFO Low Watermark (TLWM).

This read-only real time status bit will be set to a one when

the transmit FIFO contains less than the number of bytes configured by the Transmit Low Watermark Setting
control bits (TLWMS0 to TLWMS2) in the HDLC Control Register (HCR). This bit will be cleared when the FIFO
fills beyond the low watermark. The setting of this bit can cause a hardware interrupt to occur if the TLWM bit in
the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one.

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Summary of Contents for MAXIM DS3112

Page 1: ...Alarms Integrated HDLC Controller Handles LAPD Messages Without Host Intervention Integrated FEAC Controller Integrated BERT Supports Performance Monitoring T3 E3 and T1 E1 Diagnostic Tx to Rx Line Rx to Tx and Payload Loopback Supported Nonmultiplexed or Multiplexed 16 Bit Control Port with Optional 8 Bit Mode 3 3V Supply with 5V Tolerant I O Available in 256 Pin 1 27mm Pitch PBGA Package IEEE 11...

Page 2: ...CONFIGURATION AND STATUS INTERRUPT 33 4 1 MASTER RESET AND ID REGISTER DESCRIPTION 33 4 2 MASTER CONFIGURATION REGISTERS DESCRIPTION 34 4 3 MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION 38 4 3 1 Status Registers 38 4 3 2 MSR 39 4 4 TEST REGISTER DESCRIPTION 47 5 T3 E3 FRAMER 48 5 1 T3 E3 LINE LOOPBACK 48 5 2 T3 E3 DIAGNOSTIC LOOPBACK 48 5 3 T3 E3 PAYLOAD LOOPBACK 48 5 4 T3 E3 FRAMER CONTROL REG...

Page 3: ...t DR 101 11 1 6 Exit1 DR 101 11 1 7 Pause DR 101 11 1 8 Exit2 DR 101 11 1 9 Update DR 101 11 1 10 Select IR Scan 101 11 1 11 Capture IR 102 11 1 12 Shift IR 102 11 1 13 Exit1 IR 102 11 1 14 Pause IR 102 11 1 15 Exit2 IR 102 11 1 16 Update IR 102 11 2 INSTRUCTION REGISTER AND INSTRUCTIONS 103 11 2 1 SAMPLE PRELOAD 103 11 2 2 EXTEST 103 11 2 3 BYPASS 103 11 2 4 IDCODE 103 11 2 5 HIGHZ 103 11 2 6 CLA...

Page 4: ...9 E2 FRAMING STRUCTURE AND E12 MULTIPLEXING 129 14 10 E3 FRAMING STRUCTURE AND E23 MULTIPLEXING 129 14 11 G 747 BASICS 131 14 12 G 747 FRAMING STRUCTURE AND E12 MULTIPLEXING 132 15 PACKAGE INFORMATION 133 15 1 256 BALL PBGA 56 G6002 001 133 ...

Page 5: ...igure 11 2 TAP Controller State Machine 100 Figure 13 1 Low Speed T1 and E1 Port AC Timing Diagram 111 Figure 13 2 High Speed T3 and E3 Port AC Timing Diagram 112 Figure 13 3 Framer T3 and E3 Port AC Timing Diagram 113 Figure 13 4 Intel Read Cycle Nonmultiplexed 115 Figure 13 5 Intel Write Cycle Nonmultiplexed 115 Figure 13 6 Motorola Read Cycle Nonmultiplexed 116 Figure 13 7 Motorola Write Cycle ...

Page 6: ...C Characteristics 109 Table 13 1 AC Characteristics Low Speed T1 and E1 Ports 110 Table 13 2 AC Characteristics High Speed T3 and E3 Ports 112 Table 13 3 AC Characteristics Framer T3 and E3 Ports 113 Table 13 4 AC Characteristics CPU Bus Multiplexed and Nonmultiplexed 114 Table 13 5 AC Characteristics JTAG Test Port Interface 119 Table 13 6 AC Characteristics Reset and Manual Error Counter Insert ...

Page 7: ... at the HRPOS and HRNEG inputs The data is then framed by the T3 E3 framer and passed through the two step demultiplexing process to yield the resultant T1 and E1 data streams which are output at the LRCLK and LRDAT outputs In the transmit path the reverse occurs The T1 and E1 data streams are input to the device at the LTCLK and LTDAT inputs The device will sample these inputs and then multiplex ...

Page 8: ...nce 11 Network Working Group Request for Comments RFC1407 January 1993 Definition of Managed Objects for the DS3 E3 Interface Type 12 International Telecommunication Union ITU G 703 1991 Physical Electrical Characteristics of Hierarchical Digital Interfaces 13 International Telecommunication Union ITU G 823 March 1993 The Control of Jitter and Wander Within Digital Networks Which are Based on the ...

Page 9: ...es T2 E2 Alarm Indication Signal AIS and Remote Alarm Indication RAI alarms Generates Alarm Indication Signal AIS for T1 E1 data streams in both the transmit and receive directions Detects the following T2 E2 alarms and events Loss Of Frame LOF Alarm Indication Signal AIS and Remote Alarm Indication RAI Detects T1 line loopback commands C3 bit is the inverse of C1 and C2 Generates T1 line loopback...

Page 10: ...ns BPV Code Violations CV Loss Of Frame LOF framing bit errors F M or FAS EXcessive Zeros EXZ T3 Parity bits T3 C Bit Parity and Far End Block Errors FEBE Error counters can be either updated automatically on one second boundaries as timed by the DS3112 or via software control or via an external hardware pulse Can insert the following T3 E3 errors BiPolar Violations BPV EXcessive Zeros EXZ T3 Pari...

Page 11: ...IFO To BERT AIS Gen FIFO To BERT C Bit Decoding Bit Destuffing Control T2 Framer Alarm Loopback Detection T2 Framer 1 to 4 Demux 1 to 7 Demux C Bit Decoding M13 Mode Only Bit Destuffing Control Error Counters T3 Line Loopback T3 Diagnostic Loopback T3 Payload Loopback T1 Line Loopback T1 Diagnostic Loopback HDLC Controller with 256 Byte Buffer FEAC Controller Signal Inversion Control 1 2 7 7 1 2 S...

Page 12: ...4 Demux 1 to 4 Demux C Bit Decoding Bit Destuffing Control Error Counters E3 Line Loopback E3 Diagnostic Loopback E3 Payload Loopback E1 Line Loopback E1 Diagnostic Loopback HDLC Controller with 256 Byte Buffer FEAC Controller Signal Inversion Control 1 2 4 4 1 2 Signal Inversion Control Signal Inversion Control LTCLK LTDAT LTCLK LTDAT LTCLK LTDAT LTCLK LTDAT LRCLK LRDAT LRCLK LRDAT LRCLK LRDAT LR...

Page 13: ...ipolar Decoder BPV Detector T3 Framer Signal Inversion AIS Gen FIFO To BERT AIS Gen FIFO To BERT C Bit Decoding Bit Destuffing Control G747 Framer Alarm Sn Bit Detection G747 Framer 1 to 3 Demux 1 to 7 Demux C Bit Decoding M13 Mode Only Bit Destuffing Control Error Counters T3 Line Loopback T3 Diagnostic Loopback T3 Payload Loopback E1 Line Loopback E1 Diagnostic Loopback HDLC Controller with 256 ...

Page 14: ... LSB H2 CA1 I CPU Bus Address Bit 1 H1 CA2 I CPU Bus Address Bit 2 J4 CA3 I CPU Bus Address Bit 3 J3 CA4 I CPU Bus Address Bit 4 J2 CA5 I CPU Bus Address Bit 5 J1 CA6 I CPU Bus Address Bit 6 K2 CA7 I CPU Bus Address Bit 7 MSB C4 CCS I CPU Bus Chip Select Active Low C2 CD0 I O CPU Bus Data Bit 0 LSB D2 CD1 I O CPU Bus Data Bit 1 D3 CD2 I O CPU Bus Data Bit 2 E4 CD3 I O CPU Bus Data Bit 3 C1 CD4 I O...

Page 15: ...or E3 Port Transmit Clock Output A14 HTNEG O High Speed T3 or E3 Port Transmit Negative Data Output C14 HTPOS O High Speed T3 or E3 Port Transmit Positive or NRZ Data Output D7 JTCLK I JTAG IEEE 1149 1 Test Serial Clock B5 JTDI I JTAG IEEE 1149 1 Test Serial Data Input A4 JTDO O JTAG IEEE 1149 1 Test Serial Data Output A5 JTMS I JTAG IEEE 1149 1 Test Mode Select C6 JTRST I JTAG IEEE 1149 1 Test Re...

Page 16: ...rom Port 5 W3 LRDAT6 O Low Speed T1 or E1 Receive Data from Port 6 U5 LRDAT7 O Low Speed T1 or E1 Receive Data from Port 7 W5 LRDAT8 O Low Speed T1 or E1 Receive Data from Port 8 W6 LRDAT9 O Low Speed T1 or E1 Receive Data from Port 9 Y7 LRDAT10 O Low Speed T1 or E1 Receive Data from Port 10 U9 LRDAT11 O Low Speed T1 or E1 Receive Data from Port 11 W10 LRDAT12 O Low Speed T1 or E1 Receive Data fro...

Page 17: ...ort 20 T18 LTCLK21 I Low Speed T1 or E1 Transmit Clock for Port 21 P17 LTCLK22 I Low Speed T1 or E1 Transmit Clock for Port 22 P19 LTCLK23 I Low Speed T1 or E1 Transmit Clock for Port 23 N20 LTCLK24 I Low Speed T1 or E1 Transmit Clock for Port 24 M20 LTCLK25 I Low Speed T1 or E1 Transmit Clock for Port 25 K20 LTCLK26 I Low Speed T1 or E1 Transmit Clock for Port 26 J19 LTCLK27 I Low Speed T1 or E1 ...

Page 18: ... Low Speed T1 or E1 Transmit Data for Port 25 L20 LTDAT26 I Low Speed T1 or E1 Transmit Data for Port 26 J20 LTDAT27 I Low Speed T1 or E1 Transmit Data for Port 27 H19 LTDAT28 I Low Speed T1 or E1 Transmit Data for Port 28 L1 LTDATA I Low Speed T1 or E1 Transmit Data for Insert Port A M2 LTDATB I Low Speed T1 or E1 Transmit Data for Insert Port B A6 A12 A15 A20 B1 B7 B11 B12 B15 B20 C13 C15 C20 D1...

Page 19: ...e CPU Bus these signals will be outputs When writing data to the CPU Bus these signals will become inputs When the CPU bus is operated in the 8 bit mode CMS 1 CD8 to CD15 are inactive and should be tied low Signal Name CA0 to CA7 Signal Description CPU Bus Address Bus Signal Type Input These input signals determine which internal device configuration register that the external host wishes to acces...

Page 20: ... Input This active low signal must be asserted for the device to accept a read or write command from an external host Signal Name CALE Signal Description CPU Bus Address Latch Enable Signal Type Input This input signal controls a latch that exists on the CA0 to CA7 inputs When CALE is high the latch is transparent The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs I...

Page 21: ...iption T3 E3 Receive Framer Serial Data Enable or Gapped Clock Output Signal Type Output Via the DENMS control bit in Master Control Register 1 this signal can be configured to either output a data enable or a gapped clock In the data enable mode this signal will go active when payload data is available at the FRD output and it will go inactive when overhead data is being output at the FRD output ...

Page 22: ...nal Type Output This signal will be forced high when the receive T3 E3 framer is in a Loss Of Frame LOF state It will remain high as long as the LOF state persists and will return low when the framer synchronizes See Section 5 3 for details on the set and clear criteria for this signal LOF status is also available via a software bit in the T3 E3 Status Register Section 5 3 Figure 2 1 T3 E3 Receive...

Page 23: ...option is controlled via the FTCLKI control bit in Master Control Register 3 Section 4 2 Also the data input to this signal can be internally inverted if enabled via the FTDI control bit in Master Control Register 3 Section 4 2 When T3 C Bit Parity Mode is disabled C Bits are sampled at this input This signal is ignored when the M13 E13 multiplexer is enabled See the UNCHEN control bit in Master C...

Page 24: ...the process of causing errors to be inserted This signal must be returned low before any subsequent errors can be generated If this signal is not used then it should be tied low Figure 2 2 T3 E3 Transmit Formatter Timing FTCLK Inverted Mode FTD see note FTSOF Input Mode see note T3 X1 E3 Bit 1 of FAS Last Bit of the Frame FTCLK Normal Mode FTDEN Data Enable Mode for T3 see note FTDEN Data Enable M...

Page 25: ...hen the device is in the E3 Mode LRCLK17 to LRCLK28 are meaningless and should be ignored When the device is in the G 747 Mode LRCLK4 LRCLK8 LRCLK12 LRCLK16 LRCLK20 LRCLK24 and LRCLK28 are meaningless and should be ignored When the M13 E13 multiplexer is disabled then these outputs are meaningless and should be ignored Signal Name LRDATA LRDATB Signal Description Low Speed T1 or E1 Receive Drop Po...

Page 26: ...iated LTCLK This option is controlled via the LTCLKI control bit in Master Control Register 2 Section 4 2 Also the data can be internally inverted before being multiplexed if enabled via the LTDATI control bit in Master Control Register 2 Section 4 2 When the device is in the E3 Mode LTDAT17 to LTDAT28 are ignored and should be tied low When the device is in the G 747 Mode LTDAT4 LTDAT8 LTDAT12 LT...

Page 27: ... into one of the 28 T1 data streams or into one of the 16 21 E1 data streams Section 7 4 The T1 or E1 serial data streams at the associated LTDAT signals can be clocked into the device either on falling edges normal clock mode or rising edges inverted clock mode of LTCLKA LTCLKB This option is controlled via the LTCLKI control bit in Master Control Register 2 Section 4 2 When the M13 E13 multiplex...

Page 28: ...be present for the host to be able to obtain status information except the LOTC and LORC status bits see Section 4 3 from the device 2 8 High Speed T3 or E3 Transmit Port Signal Description Signal Name HTPOS HTNEG Signal Description High Speed T3 or E3 Transmit Serial Data Outputs Signal Type Output These output signals present the outgoing T3 data streams or E3 data streams Data can be clocked ou...

Page 29: ...is action will set the device into the boundary scan bypass mode allowing normal device operation If boundary scan is not used this signal should be held low This signal has an internal pullup Signal Name JTMS Signal Description JTAG IEEE 1149 1 Test Mode Select Signal Type Input with internal 10kΩ pullup This signal is sampled on the rising edge of JTCLK and is used to place the test port into th...

Page 30: ...3112 This signal should be set into the proper state before a hardware reset is issued via the RST signal This input is coupled with the T3E3MS input to create a special test mode whereby all the outputs are tri stated Table 2 3 0 T3 Mode 1 G 747 Mode Table 2 3 Mode Select Decode T3E3MS G 747E MODE SELECTED 0 0 T3 or M13 Operation 0 1 G 747 Operation 1 0 E3 or E13 Operation 1 1 Special Test Mode t...

Page 31: ...eceive Path AIS Generation Control Register 1 6 4 42 T1E1RAIS2 R W T1 E1 Receive Path AIS Generation Control Register 2 6 4 44 T1E1TAIS1 R W T1 E1 Transmit Path AIS Generation Control Register 1 6 4 46 T1E1TAIS2 R W T1 E1 Transmit Path AIS Generation Control Register 2 6 4 50 T1E1LLB1 R W T1 E1 Line Loopback Control Register 1 7 1 52 T1E1LLB2 R W T1 E1 Line Loopback Control Register 2 7 1 54 T1E1D...

Page 32: ...nsmit HDLC FIFO Register 9 2 86 HSR R HDLC Status Register 9 3 88 IHSR R W Interrupt Mask Register for HSR 9 3 90 FCR R W FEAC Control Register 10 1 92 FSR R FEAC Status Register 10 2 38 48 64 66 68 94 96 98 0E 1A 1C 1E 2C 2E 3A 3C 3E 4A 4C 4E 6A 6C 8A 8C 8E 9A 9C 9E Not Assigned Addresses A0 to FF are not assigned ...

Page 33: ...o send an all ones pattern This bit must be set high for a minimum of 100ns This software bit is logically ORed with the hardware signal RST 0 normal operation 1 force all internal registers to their default value of 0000h Bit 1 Low Speed T1 E1 Receive FIFO Reset RFIFOR A zero to one transition on this bit will cause the receive T1 E1 demux FIFOs to be reset which will cause them to be flushed See...

Page 34: ...ock Figure 1 1 This bit should not be set low in the T3 unchannelized mode UNCHEN 1 When this bit is set high C Bit Parity mode is enabled and the C bits are sourced from the T3 framer block Figure 1 1 and Figure 1 3 0 disable C Bit Parity mode also known as the M23 Mode 1 enable C Bit Parity mode Bit 3 Automatic One Second Error Counters Update Defeat AECU When this bit is set low the device will...

Page 35: ...will pulse for one FTCLK cycle at the beginning of each frame When this bit is high the FTSOF signal is an input and the device uses it to determine the frame boundaries 0 FTSOF is an output 1 FTSOF is an input Bit 8 Low Speed T1 E1 Transmit Port Common Clock Enable LTCCEN When this bit is set high the LTCLK1 to LTCLK28 and LTCLKA and LTCLKB inputs are ignored and a common clock sourced via the LT...

Page 36: ... Disable HTDATH Note that this bit must be set by the host in order for T3 E3 traffic to be output from the device 0 force the HTPOS and HTNEG signals high force high mode 1 allow normal transmit data to appear at the HTPOS and HTNEG signals normal mode Bit 5 HTPOS HTNEG Force Low Enable HTDATL 0 allow normal transmit data to appear at the HTPOS and HTNEG signals normal mode 1 force the HTPOS and ...

Page 37: ...e FTD signal inverted mode Bit 2 FTCLK Invert Enable FTCLKI 0 do not invert the FTCLK signal normal mode 1 invert the FTCLK signal inverted mode Bit 3 FTSOF Invert Enable FTSOFI 0 do not invert the FTSOF signal normal mode 1 invert the FTSOF signal inverted mode Bit 4 FRDEN Invert Enable FRDENI 0 do not invert the FRDEN signal normal mode 1 invert the FRDEN signal inverted mode Bit 5 FRD Invert En...

Page 38: ...sserted An example of an event status bit is the one second timer boundary occurrence OST The second type of status bit is called an alarm status bit which is derived from conditions that can occur for longer than an instance The alarm status bits will be cleared when read unless the alarm is still present The alarm status bits generate interrupts on a change in state in the alarm i e when it is a...

Page 39: ... the HRCLK signal This bit will be cleared when read and will not be set again until another one second boundary has occurred The setting of this status bit can cause a hardware interrupt to occur if the OST bit in the Interrupt Mask for MSR IMSR register is set to a one The interrupt will be allowed to clear when this bit is read Bit 1 Counter Overflow Event COVF This latched read only event stat...

Page 40: ...rrupt will be allowed to clear when the T2E2SR1 register is read see Figure 4 6 Bit 6 Change in T2 E2 RAI Status T2E2SR2 This read only real time status bit will be set to a one when one or more of the T2 E2 G 747 framers have detected a change in the detection of the Remote Alarm Indication RAI signal and the interrupt enable bit 7 is set in the T2E2SR2 register See the T2E2SR2 register descripti...

Page 41: ...ts will be set and then immediately cleared if the clock is present Bit 12 State of the T3E3MS Input Signal T3E3MS This read only real time status bit reflects the current state of the external T3E3MS input signal This status bit cannot generate an interrupt Bit 13 State of the G 747E Input Signal G 747E This read only real time status bit reflects the current state of the external G 747E input si...

Page 42: ...atch RPE HSR Bit 6 Internal Receive Packet End Signal from HDLC Event Latch Internal Transmit FIFO Underrun Signal from HDLC Event Latch Internal Receive FIFO Overrun Signal from HDLC TUDR HSR Bit 7 ROVR HSR Bit 13 Mask RPE IHSR Bit 6 Mask Mask TUDR IHSR Bit 3 ROVR IHSR Bit 13 Event Latch Internal Receive Abort Detect Signal from HDLC RABT HSR Bit 15 Mask RABT IHSR Bit 15 Event Latch Transmit Pack...

Page 43: ...2E2SR1 Bit 6 Alarm Latch Change in State Detect AIS1 T2E2SR1 Bit 8 Internal AIS Signal from T2 E2 Framer 1 Alarm Latch Change in State Detect Internal AIS Signal from T2 E2 Framer 2 Alarm Latch Change in State Detect Internal AIS Signal from T2 Framer 7 OR Mask IEAIS T2E2SR1 Bit 15 AIS2 T2E2SR1 Bit 9 AIS7 T2E2SR1 Bit 14 Mask T2E2SR1 IMSR Bit 5 INT Hardware Signal T2E2SR1 Status Bit MSR Bit 5 Event...

Page 44: ... 1 RAI7 T2E2SR2 Bit 6 Mask T2E2SR2 IMSR Bit 6 INT Hardware Signal T2E2SR2 Status Bit MSR Bit 6 Event Latch Event Latch Event Latch NOTE ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR2 REGISTER IS READ Figure 4 8 T1LB Status Bit Flow LLB1 T1LBSR1 Bit 0 Internal T1 Loopback Command Signal from T2 E2 Framer OR Mask T1LB IMSR Bit 8 INT Hardware Signal T1LB Status Bit MSR Bit 8 LLB2 T1LB...

Page 45: ... AIS IT3E3SR Bit 2 Change in State Detect Alarm Latch Receive RAI Signal from T3 E3 Framer AIS T3E3SR Bit 3 Mask AIS IT3E3SR Bit 3 Change in State Detect Alarm Latch Receive Idle Signal from T3 E3 Framer T3IDLE T3E3SR Bit 4 Mask T3IDLE IT3E3SR Bit 4 Change in State Detect Event Latch Receive Start Of Frame Signal from T3 E3 Framer RSOF T3E3SR Bit 5 Mask RSOF IT3E3SR Bit 5 Event Latch Transmit Star...

Page 46: ...s BERT 0 interrupt masked 1 interrupt unmasked Bit 3 Change in HDLC Status HDLC 0 interrupt masked 1 interrupt unmasked Bit 4 Change in FEAC Status FEAC 0 interrupt masked 1 interrupt unmasked Bit 5 Change in T2 E2 LOF or AIS Status T2E2SR1 0 interrupt masked 1 interrupt unmasked Bit 6 Change in T2 E2 RAI Status T2E2SR2 0 interrupt masked 1 interrupt unmasked Bit 8 T1 Loopback Detected T1LB 0 inte...

Page 47: ...h Bit 7 6 5 4 3 2 1 0 Name FT5 FT4 FT3 FT2 FT1 FT0 Default 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default Bits 0 to 5 Factory Test Bits FT0 to FT5 These bits are used by the factory to place the DS3112 into the test mode For normal device operation these bits should be set to zero whenever this register is written to ...

Page 48: ...NEG inputs directly back to the transmit side the HTCLK HTPOS and HTNEG outputs When this loopback is enabled the incoming receive data continues to pass through the device but the data output from the T3 E3 formatter is replaced with the data being input to the device See the block diagrams in Section 1 for a visual description of this loopback 5 2 T3 E3 Diagnostic Loopback The diagnostic loopbac...

Page 49: ...e RAI bit will be set to a zero 0 do not transmit RAI 1 transmit RAI Bit 2 T3 E3 Transmit Pass Through Enable TPT 0 enable the framer to insert framing and overhead bits 1 framer will not insert any framing or overhead bits Bits 3 and 4 E3 National Bit Control Bits 0 and 1 E3SnC0 and E3SnC1 These bits determine from where the E3 national bit is sourced On the receive side the Sn bit is always rout...

Page 50: ...nd these include the following Frame Error Counter when it is configured to count frame errors not LOF occurrences T3 Parity Bit Error Counter T3 C Bit Parity Error Counter T3 Far End Block Error or E3 RAI Counter When this bit is set low these error counters will not be allowed to increment during LOF conditions When this bit is set high these error counters will be allowed to increment during LO...

Page 51: ...o the transmit data stream A T3 parity event is defined as flipping the proper polarity of both the P bits in a T3 Frame See Section 14 5 for details about the P bits Once this bit has been toggled from a zero to a one the device waits for the next T3 frame to flip both P bits This bit must be cleared and set again for a subsequent error to be inserted Toggling this bit has no affect when the devi...

Page 52: ...tion 1 1 T3 Mode Three consecutive M bit errors causes the far end to lose synchronization E3 Mode Four consecutive FAS words of 0000101111 are generated instead of the normal FAS word which is 1111010000 i e all FAS bits are inverted causes the far end to lose synchronization Bit 7 Manual Error Insert Mode Select MEIMS When this bit is set low the device will insert errors on each 0 to 1 transiti...

Page 53: ...ion can cause a hardware interrupt to occur if the AIS bit in the Interrupt Mask for T3E3SR IT3E3SR register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR IMSR register is set to a one The interrupt will be allowed to clear when this bit is read The AIS alarm detection criteria is described in Table 5 1 and Table 5 2 Bit 3 Remote Alarm Indication Detected RAI This latched read o...

Page 54: ...arm Latch Receive LOS Signal from T3 E3 Framer LOS T3E3SR Bit 0 Mask LOS IT3E3SR Bit 0 Change in State Detect Alarm Latch Receive LOF Signal from T3 E3 Framer LOF T3E3SR Bit 1 Mask LOF IT3E3SR Bit 1 Change in State Detect Alarm Latch Receive AIS Signal from T3 E3 Framer AIS T3E3SR Bit 2 Mask AIS IT3E3SR Bit 2 Change in State Detect Alarm Latch Receive RAI Signal from T3 E3 Framer RAI T3E3SR Bit 3 ...

Page 55: ...l Occurrence LOS 0 interrupt masked 1 interrupt unmasked Bit 1 Loss Of Frame Occurrence LOF 0 interrupt masked 1 interrupt unmasked Bit 2 Alarm Indication Signal Detected AIS 0 interrupt masked 1 interrupt unmasked Bit 3 Remote Alarm Indication Detected RAI 0 interrupt masked 1 interrupt unmasked Bit 4 T3 Idle Signal Detected T3IDLE 0 interrupt masked 1 interrupt unmasked Bit 5 Transmit T3 E3 Star...

Page 56: ...e or more F bits in error out of 16 consecutive or 2 or more M bits in error out of four consecutive Synchronization occurs RAI Note 1 Remote Alarm Indication This is also referred to as SEF AIS in Bellcore GR 820 Inactive X1 X2 1 Active X1 X2 0 X1 and X2 0 for four consecutive M frames 426µs X1 and X2 1 for four consecutive M frames 426µs Idle Signal Properly framed 1100 pattern which is aligned ...

Page 57: ...ifferent alignment than it had previously If the device has never acquired synchronization before then this status bit is meaningless This bit will be cleared when read and will not be set again until the framer has lost synchronization and reacquired synchronization in a different alignment Bit 1 Zero Suppression Codeword Detected ZSCD This latched read only event status bit will be set to a one ...

Page 58: ...vent status bit will be set to a one each time the T3 E3 framer exits a Loss Of Signal LOS state This bit will be cleared when read and will not be set again until the device once again exits the LOS state The LOS alarm criteria are described in Table 5 1 and Table 5 2 This status bit is useful in helping the host determine if the LOS persists as defined in ANSI T1 231 Bit 11 Loss Of Frame Clear D...

Page 59: ...V0 to BPV15 These bits report the number of BiPolar Violations BPV In the E3 Mode this counter can also be configured via the E3CVE bit in the T3E3 Control Register Section 5 2 to count Code Violations CV A BPV is defined as consecutive pulses or marks of the same polarity that are not part of a B3ZS HDB3 codeword A CV is defined in ITU O 161 as consecutive BPVs of the same polarity Register Name ...

Page 60: ...M Bit Errors E3 Mode Illegal State When the FECR is configured to count LOF occurrences the FECR increments by one each time the device loses receive synchronization When the FECR is configured to count framing bit errors it can be configured via the ECC control bit in the T3 E3 Control Register Section 5 2 to either continue counting frame bit errors during a LOF or not Register Name PCR Register...

Page 61: ...ntinue counting C bit parity bit errors during a LOF or not Register Name FEBECR Register Description T3 Far End Block Error or E3 RAI Count Register Register Address 2Ah Bit 7 6 5 4 3 2 1 0 Name FEBE7 FEBE6 FEBE5 FEBE4 FEBE3 FEBE2 FEBE1 FEBE0 Default Bit 15 14 13 12 11 10 9 8 Name FEBE15 FEBE14 FEBE13 FEBE12 FEBE11 FEBE10 FEBE9 FEBE8 Default Note Bits that are underlined are read only all other b...

Page 62: ...re the device to pass normal traffic via the T1E1RAIS1 T1E1RAIS2 T1E1TAIS1 and T1E1TAIS2 registers Section 6 4 6 2 T2 E2 G 747 Framer Control Register Description Register Name T2E2CR1 Register Description T2 E2 Control Register 1 Register Address 30h Bit 7 6 5 4 3 2 1 0 Name TRAI7 TRAI6 TRAI5 TRAI4 TRAI3 TRAI2 TRAI1 Default 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name TAIS7 TAIS6 TAIS5 TAIS4 TAIS...

Page 63: ...it errors to cause the far end to lose frame synchronization This bit must be cleared and set again for a subsequent set of errors to be generated MODE FRAMING ERRORS GENERATED T3 Mode Four consecutive F bit errors E3 Mode Four consecutive FAS words of 0000101111 generated instead of the normal FAS word which is 1111010000 i e all FAS bits are inverted G 747 Mode Four consecutive FAS words of 0001...

Page 64: ...d be set to one if the host wishes to have T2 E2 G 747 LOF occurrences cause a hardware interrupt or the setting of the T2E2SR1 status bit in the MSR register Figure 6 1 The T2E2SR1 bit in the Interrupt Mask for the Master Status Register IMSR must also be set to one for an interrupt to occur 0 interrupt masked 1 interrupt unmasked Bits 8 to 14 Alarm Indication Signal Detected AISn when n 1 to 7 T...

Page 65: ...2E2SR1 Bit 6 Alarm Latch Change in State Detect AIS1 T2E2SR1 Bit 8 Internal AIS Signal from T2 E2 Framer 1 Alarm Latch Change in State Detect Internal AIS Signal from T2 E2 Framer 2 Alarm Latch Change in State Detect Internal AIS Signal from T2 Framer 7 OR Mask IEAIS T2E2SR1 Bit 15 AIS2 T2E2SR1 Bit 9 AIS7 T2E2SR1 Bit 14 Mask T2E2SR1 IMSR Bit 5 INT Hardware Signal T2E2SR1 Status Bit MSR Bit 5 Event...

Page 66: ...should be set to one if the host wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the T2E2SR2 status bit in the MSR register Figure 6 2 The T2E2SR2 bit in the Interrupt Mask for the Master Status Register IMSR must also be set to one for an interrupt to occur 0 interrupt masked 1 interrupt unmasked Bits 8 to 11 E2 Receive National Bit E2Snn when n 1 to 4 This r...

Page 67: ...os in each of two consecutive 848 bit frames Five or more zeros in each of two consecutive 848 bit frames LOF Loss Of Frame Too many FAS errors Four consecutive bad FAS Three consecutive good FAS RAI Remote Alarm Indication Inactive Bit 11 of the frame 0 Active Bit 11 of the frame 1 Bit 11 1 for four consecutive frames 3392 bits Bit 11 0 for four consecutive frames 3392 bits Table 6 3 G 747 Alarm ...

Page 68: ... to 15 Receive AIS Generation Control for T1 E1 Ports 1 to 16 AIS1 to AIS2 These bits determine whether the device will replace the demultiplexed T1 E1 data stream with an unframed all ones AIS signal AIS1 controls the data at LRDAT1 AIS2 controls the data at LRDAT2 and so on Since ports 4 8 12 16 20 24 and 28 are not active in the G 747 mode the AIS4 AIS8 AIS12 and AIS16 bits have no affect in th...

Page 69: ...hrough to the multiplexer Register Name T1E1TAIS2 Register Description T1 E1 Transmit Path AIS Generation Control Register 2 Register Address 46h Bit 7 6 5 4 3 2 1 0 Name AIS24 AIS23 AIS22 AIS21 AIS20 AIS19 AIS18 AIS17 Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name AIS28 AIS27 AIS26 AIS25 Default 0 0 0 0 Note Bits that are underlined are read only all other bits are read write Bits 0 to 11...

Page 70: ...the T1E1DLB1 and T1E1DLB2 control registers Section 7 5 7 3 T1 Line Loopback Command M13 systems have the ability to request that a T1 line be looped back which is achieved by inverting the C3 bit See Section 14 2 for details on M13 formats and operation The DS3112 will detect when the C3 bit has been inverted and will indicate which T1 line is being requested to be placed into line loopback via t...

Page 71: ...he LLB4 LLB8 LLB12 and LLB16 bits have no effect in the G 747 mode 0 disable loopback 1 enable loopback Register Name T1E1LLB2 Register Description T1 E1 Line Loopback Control Register 2 Register Address 52h Bit 7 6 5 4 3 2 1 0 Name LLB24 LLB23 LLB22 LLB21 LLB20 LLB19 LLB18 LLB17 Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name LLB28 LLB27 LLB26 LLB25 Default 0 0 0 0 Note Bits that are under...

Page 72: ...LB16 bits have no effect in the G 747 mode 0 disable loopback 1 enable loopback Register Name T1E1DLB2 Register Description T1 E1 Diagnostic Loopback Control Register 2 Register Address 56h Bit 7 6 5 4 3 2 1 0 Name DLB24 DLB23 DLB22 DLB21 DLB20 DLB19 DLB18 DLB17 Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name DLB28 DLB27 DLB26 DLB25 Default 0 0 0 0 Note Bits that are underlined are read onl...

Page 73: ...e appropriate T2 transmit formatter to generate a Line Loopback command for the far end When this bit is set high the T2 transmit formatter will force the C3 bit to be the inverse of the C1 and C2 bits The T2 transmit formatter will continue to force the C3 bit to be the inverse of the C1 and C2 bits as long as this bit is held high When this bit is set low C3 will match the C1 and C2 bits LB1 cor...

Page 74: ...iate T2 transmit formatter to generate a Line Loopback command for the far end When this bit is set high the T2 transmit formatter will force the C3 bit to be the inverse of the C1 and C2 bits The T2 transmit formatter will continue to force the C3 bit to be the inverse of the C1 and C2 bits as long as this bit is held high When this bit is set low C3 will match the C1 and C2 bits LB17 corresponds...

Page 75: ... or T1LBSR2 can cause a hardware interrupt to occur if the T1LB bit in the Interrupt Mask for MSR IMSR is set to a one In the E3 and G 747 modes these bits are meaningless and should be ignored Register Name T1LBSR2 Register Description T1 Line Loopback Command Status Register 2 Register Address 5Eh Bit 7 6 5 4 3 2 1 0 Name LLB24 LLB23 LLB22 LLB21 LLB20 LLB19 LLB18 LLB17 Default Bit 15 14 13 12 11...

Page 76: ...Default 0 0 0 0 0 Note Bits that are underlined are read only all other bits are read write Bits 0 to 4 T1 E1 Drop Port A Select Bits DPAS0 to DPAS4 Bits 8 to 12 T1 E1 Drop Port B Select Bits DPBS0 to DPBS4 These bits select which of the 28 T1 ports or 16 E1 ports if any should be output at either Drop Port A or Drop Port B If no port is selected the LRDATA LRCLKA LRDATB and LRCLKB output pins wil...

Page 77: ...Insert Port A or Insert Port B should replace the clock and data presented at one of the 28 T1 ports or 16 21 E1 ports If no port is selected the clock and data presented at the LTDATA LTCLKA LTDATB and LTCLKB input pins is ignored The same port should not be selected for both Insert Port A and Insert Port B IPxS4 0 00000 No Port 01000 Port 8 10000 Port 16 11000 Port 24 00001 Port 1 01001 Port 9 1...

Page 78: ...C Register Description BERT Mux Control Register Register Address 0x6Eh Bit 7 6 5 4 3 2 1 Name RBPS3 RBPS2 RBPS1 0 RBPS4 RBPS0 Default 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name TBPS4 TBPS3 TBPS2 TBPS1 TBPS0 Default 0 0 0 0 0 Note Bits that are underlined are read only all other bits are read write Bits 0 to 4 Receive BERT Port Select Bits 0 to 4 RBPS0 to RBPS4 These bits determine if data from any ...

Page 79: ...n data from the transmit BERT is placed into all bit positions of the T3 E3 data stream payload and the overhead bits TBPS4 0 00000 No Data 01000 Port 8 00001 Port 1 01001 Port 9 00010 Port 2 01010 Port 10 00011 Port 3 01011 Port 11 00100 Port 4 01100 Port 12 00101 Port 5 01101 Port 13 00110 Port 6 01110 Port 14 00111 Port 7 01111 Port 15 10000 Port 16 11000 Port 24 10001 Port 17 11001 Port 25 100...

Page 80: ...unt This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period Must be cleared and set again for a subsequent loads Bits 2 to 4 Pattern Select Bits 0 PS0 to PS2 If PBS 0 000 Pseudorandom Pattern 27 1 ANSI T1 403 1999 Annex B 001 Pseudorandom Pattern 220 1 non QRSS 1 invert the outgoing data stream 001 Pseudorandom Pattern 211 1 ITU O 153 010 Pseudorandom...

Page 81: ...ength Code 17 Bits 0000 18 Bits 0001 19 Bits 0010 20 Bits 0011 21 Bits 0100 22 Bits 0101 23 Bits 0110 24 Bits 0111 25 Bits 1000 1001 27 Bits 1010 28 Bits 1011 29 Bits 1100 30 Bits 31 Bits 1101 32 Bits 1111 Bit 13 Interrupt Enable for Counter Overflow IEOF Allows the receive BERT to cause an interrupt if either the Bit Counter or the Error Counter overflows 0 interrupt masked 1 interrupt enabled Bi...

Page 82: ...ng error detection operation EIB2 EIB1 EIB0 ERROR RATE INSERTED 0 0 0 No errors automatically inserted 0 0 1 10 1 1 error per 10 bits 0 1 0 10 2 1 error per 100 bits 0 1 1 10 3 1 error per 1kbits 1 0 0 10 4 1 error per 10kbits 1 0 1 10 5 1 error per 100kbits 1 1 0 10 6 1 error per 1Mbits 1 1 1 10 7 1 error per 10Mbits Bits 8 to 15 Alternating Word Count Rate AWC0 to AWC7 When the BERT is programme...

Page 83: ...st be properly loaded for the BERT to properly generate and synchronize to either a repetitive pattern a pseudorandom pattern or a alternating word pattern For a repetitive pattern that is less than 17 bits then the pattern should be repeated so that all 32 bits are used to describe the pattern For example if the pattern was the repeating 5 bit pattern 01101 where rightmost bit is one sent first a...

Page 84: ...y all other bits are read write Bits 0 to 31 BERT 32 Bit Bit Counter BBC0 to BBC31 This 32 bit counter will increment for each data bit i e clock received This counter is not disabled when the receive BERT loses synchronization This counter can be cleared by toggling the LC control bit in BERTC0 This counter saturates and will not rollover Upon saturation the BBCO status bit in the BERTEC0 registe...

Page 85: ...upt to occur if the IEOF bit in BERT Control Register 0 is set to a one and the BERT bit in the Interrupt Mask for MSR IMSR register is set to a one The interrupt will be allowed to clear when this bit is read Figure 8 1 Bit 3 Bit Error Detected BED A latched read only event status bit that is set when a bit error is detected The receive BERT must be in synchronization for it to detect bit errors ...

Page 86: ...20 BEC19 BEC18 BEC17 BEC16 Default 0 0 0 0 0 0 0 0 Note Bits that are underlined are read only all other bits are read write Bits 0 to 15 BERT 24 Bit Error Counter BEC8 to BEC23 Upper two bytes of the 24 bit counter This 24 bit counter will increment for each data bit received in error This counter is not disabled when the receive BERT loses synchronization This counter can be cleared by toggling ...

Page 87: ...epting packets until either the FIFO is completely emptied or reset If the receive HDLC controller ever detects an incoming abort seven or more ones in a row it will set the Receive Abort Sequence Detected RABT status bit If an abort sequence is detected in the middle of an incoming packet then the receive HDLC controller will set the Packet Status bits accordingly The receive HDLC has been design...

Page 88: ...egister Register Address 80h Bit 7 6 5 3 2 1 0 Name RHR THR TFS TZSD TCRCD Default 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name RHWMS2 RHWMS1 RHWMS0 TLWMS2 TLWMS1 TLWMS0 RID TID Default 0 0 0 0 0 0 0 0 Note Bits that are underlined are read only all other bits are read write Bit 0 Transmit CRC Defeat TCRCD When this bit is set low the HDLC will automatically calculate and append the 16 bit CRC to the ...

Page 89: ...invert all data Bit 9 Receive Invert Data RID The control bit determines whether all of the data into the HDLC controller including flags and CRC checksum will be inverted before processing 0 do not invert data normal operation 1 invert all data Bits 10 to 12 Transmit Low Watermark Select Bits TLWMS0 to TLWMS2 These control bits determine when the HDLC controller should set the TLWM status bit in ...

Page 90: ... will be reported as PS0 0 PS1 1 and the data in the FIFO should be ignored Bits 0 to 7 Receive FIFO Data D0 to D7 Data from the Receive FIFO can be read from these bits D0 is the LSB and is received first while D7 is the MSB and is received last Bit 8 Opening Byte OBYTE This bit will be set to a one when the byte available at the D0 to D7 bits from the Receive FIFO is the first byte of a HDLC pac...

Page 91: ...ription HDLC Status Register Register Address 86h Bit 7 6 5 4 3 2 1 0 Name TUDR RPE RPS RHWM TLWM TEND Default Bit 15 14 13 12 11 10 9 8 Name RABT REMPTY ROVR TEMPTY TFL3 TFL2 TFL1 TFL0 Default Note See Figure 9 1 for details on the signal flow for the status bits in the HSR register Bits that are underlined are read only all other bits are read write Bit 0 Transmit Packet End TEND This latched re...

Page 92: ... and the HDLC bit in the Interrupt Mask for MSR IMSR register is set to a one The interrupt will be allowed to clear when this bit is read Bit 7 Transmit FIFO Underrun TUDR This latched read only event status bit will be set to a one each time the transmit FIFO underruns and an abort is automatically sent This bit will be cleared when read and will not be set again until another underrun occurs i ...

Page 93: ...quence Detected RABT This latched read only event status bit will be set to a one each time the receive HDLC controller detects seven or more ones in a row during packet reception If the receive HDLC is not currently receiving a packet then seven or more ones in a row will not trigger this status bit This bit will be cleared when read and will not be set again until another abort is detected at le...

Page 94: ...atch RPE HSR Bit 6 Internal Receive Packet End Signal from HDLC Event Latch Internal Transmit FIFO Underrun Signal from HDLC Event Latch Internal Receive FIFO Overrun Signal from HDLC TUDR HSR Bit 7 ROVR HSR Bit 13 Mask RPE IHSR Bit 6 Mask Mask TUDR IHSR Bit 7 ROVR IHSR Bit 13 Event Latch Internal Receive Abort Detect Signal from HDLC RABT HSR Bit 15 Mask RABT IHSR Bit 15 Event Latch Transmit Pack...

Page 95: ...pt masked 1 interrupt unmasked Bit 2 Transmit FIFO Low Watermark TLWM 0 interrupt masked 1 interrupt unmasked Bit 4 Receive FIFO High Watermark RHWM 0 interrupt masked Bit 13 Receive FIFO Overrun ROVR 1 interrupt unmasked Bit 5 Receive Packet Start RPS 0 interrupt masked 1 interrupt unmasked Bit 6 Receive Packet End RPE 0 interrupt masked 1 interrupt unmasked Bit 7 Transmit FIFO Underrun TUDR 0 in...

Page 96: ...ten into the Receive FEAC FIFO for the host to read The host can use the RFCD status to know when to read the Receive FEAC FIFO The Receive FEAC FIFO is four codewords deep If the FIFO is full when the receive FEAC detector attempts to write a new incoming codeword the latest incoming codeword s will be discarded and the Receive FEAC FIFO Overflow RFFO status bit will be set 90h The DS3112 can tra...

Page 97: ...rm 0xxxxxx011111111 where the rightmost bit is transmitted first These six bits are the middle six bits of the second byte of the FEAC codeword i e the six x bits The device can generate two different codewords and these six bits represent what will be transmitted for codeword B TFCB0 is the LSB and is transmitted first while TFCB5 is the MSB and is transmitted last The TFS0 and TFS1 control bits ...

Page 98: ...Receive FEAC Idle RFI This latched read only event status bit will be set to a one each time the FEAC controller has detected 16 consecutive ones following a valid codeword This bit will be cleared when read The setting of this bit can cause a hardware interrupt to occur if the IERFI bit in the FEAC Control Register FCR is set to one and the FEAC bit in the Interrupt Mask for MSR IMSR is set to on...

Page 99: ...nstruction Register Bypass Register Boundary Scan Register Device Identification Register The Test Access Port has the necessary interface pins namely JTCLK JTRST JTDI JTDO and JTMS Details on these pins can be found in Section 2 9 Details on the Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149 1 1990 IEEE 1149 1a 1993 and IEEE 1149 1b 1994 Figure 11 1 JTAG Block Diagr...

Page 100: ...oller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK Figure 11 2 TAP Controller State Machine Test Logic Reset Run Test Idle Select DR Scan 1 0 Capture DR 1 0 Shift DR 0 1 Exit1 DR 1 0 Pause DR 1 Exit2 DR 1 Update DR 0 0 1 Select IR Scan 1 0 Capture IR 0 Shift IR 0 1 Exit1 IR 1 0 Pause IR 1 Exit2 IR 1 Update IR 0 0 1 0 0 1 0 1 0 1 ...

Page 101: ...intain its previous state 11 1 6 Exit1 DR While in this state a rising edge on JTCLK with JTMS high will put the controller in the Update DR state which terminates the scanning process A rising edge on JTCLK with JTMS low will put the controller in the Pause DR state 11 1 7 Pause DR Shifting of the Test registers is halted while in this state All Test registers selected by the current instruction ...

Page 102: ...or every rising edge of JTCLK towards the serial output The parallel register as well as all Test registers remain at their previous states A rising edge on JTCLK with JTMS high will move the controller to the Exit1 IR state A rising edge on JTCLK with JTMS low will keep the controller in the Shift IR state while moving data one stage through the Instruction shift register 11 1 13 Exit1 IR A risin...

Page 103: ...ter via JTDI using the Shift DR state 11 2 2 EXTEST EXTEST allows testing of all interconnections to the DS3112 When the EXTEST instruction is latched in the instruction register the following actions occur Once enabled via the Update IR state the parallel outputs of all digital output pins will be driven The Boundary Scan register will be connected between JTDI and JTDO The Capture DR will sample...

Page 104: ...entification Register The Identification register contains a 32 bit shift register and a 32 bit latched parallel output This register is selected during the IDCODE instruction and when the TAP controller is in the Test Logic Reset state Boundary Scan Register This register contains both a shift register path and a latched parallel output for all control cells and digital I O cells and is 196 bits ...

Page 105: ...LTDAT28 H19 I 38 LRCLK28 H20 O 39 LRDAT28 J18 O 40 LTCLK27 J19 I 41 LTDAT27 J20 I 42 LRCLK27 K18 O 43 LRDAT27 K19 O 44 LTCLK26 K20 I 45 LTDAT26 L20 I 46 LRCLK26 L18 O 47 LRDAT26 L19 O 48 LTCLK25 M20 I 49 LTDAT25 M19 I 50 LRCLK25 M18 O 51 LRDAT25 M17 O 52 LTCLK24 N20 I 53 LTDAT24 N19 I 54 LRCLK24 N18 O 55 LRDAT24 P20 O 56 LTCLK23 P19 I 57 LTDAT23 P18 I 58 LRCLK23 R20 O 59 LRDAT23 R19 O 60 LTCLK22 P...

Page 106: ... Y16 O 87 LRDAT16 W15 O 88 LTCLK15 V14 I 89 LTDAT15 Y15 I 90 LRCLK15 W14 O 91 LRDAT15 Y14 O 92 LTCLK14 V13 I 93 LTDAT14 W13 I 94 LRCLK14 Y13 O 95 LRDAT14 V12 O 96 LTCLK13 W12 I 97 LTDAT13 Y12 I 98 LRCLK13 V11 O 99 LRDAT13 W11 O 100 LTCLK12 Y11 I 101 LTDAT12 Y10 I 102 LRCLK12 V10 O 103 LRDAT12 W10 O 104 LTCLK11 Y9 I 105 LTDAT11 W9 I 106 LRCLK11 V9 O 107 LRDAT11 U9 O 108 LTCLK10 Y8 I 109 LTDAT10 W8 ...

Page 107: ... U2 O 135 LRDAT4 T3 O 136 LTCLK3 U1 I 137 LTDAT3 T2 I 138 LRCLK3 R3 O 139 LRDAT3 P4 O 140 LTCLK2 R2 I 141 LTDAT2 P3 I 142 LRCLK2 R1 O 143 LRDAT2 P2 O 144 LTCLK1 P1 I 145 LTDAT1 N3 I 146 LRCLK1 N2 O 147 LRDAT1 N1 O 148 LTCLKB M3 I 149 LTDATB M2 I 150 LRCLKB M1 O 151 LRDATB L3 O 152 LTCLKA L2 I 153 LTDATA L1 I 154 LRCLKA K1 O 155 LRDATA K3 O 156 CA7 K2 I 157 CA6 J1 I 158 CA5 J2 I 159 CA4 J3 I 160 CA...

Page 108: ...IN G4 I 176 CD9_OUT F3 O 177 CD9_IN F3 I 178 CD8_OUT E1 O 179 CD8_IN E1 I 180 CD7_OUT E2 O 181 CD7_IN E2 I 182 CD6_OUT E3 O 183 CD6_IN E3 I 184 CD5_OUT D1 O 185 CD5_IN D1 I 186 CD4_OUT C1 O 187 CD4_IN C1 I 188 CD3_OUT E4 O 189 CD3_IN E4 I 190 CD2_OUT D3 O 191 CD2_IN D3 I 192 CD1_OUT D2 O 193 CD1_IN D2 I 194 CD0_OUT C2 O 195 CD0_IN C2 I 196 CD_ENB_N Control bit 1 CD is an input 0 CD is an output ...

Page 109: ...lute maximum rating conditions for extended periods of time can affect reliability Table 1 1 Recommended DC Operating Conditions TA 0 C to 70 C for DS3112 TA 40 C to 85 C for DS3112N PARAMETER SYMBOL MIN TYP MAX NOTES Logic 1 VIH 2 2 5 5 V Logic 0 VIL 0 3 0 8 V Supply VDD 3 135 3 465 V Table 1 2 DC Characteristics 2 VDD 3 3V 5 TA 0 C to 70 C for DS3112 TA 40 C to 85 C for DS3112N PARAMETER SYMBOL ...

Page 110: ...s LTDAT Setup Time to the Falling Edge or Rising Edge of LTCLK LTCCLK t4 50 ns LTDAT Hold Time from the Falling Edge or Rising Edge of LTCLK LTCCLK t5 50 ns Delay from the Rising Edge or Falling Edge of LRCLK to Data Valid on LRDAT t6 50 ns Delay from the Rising Edge or Falling Edge of LRCCLK to Data Valid on LRDAT t6 100 ns 5 NOTES 1 T3 mode 2 E3 mode 3 In normal mode LTDAT is sampled on the fall...

Page 111: ...DS3112 111 of 133 Figure 13 1 Low Speed T1 and E1 Port AC Timing Diagram LRDAT LTDAT t4 t5 t6 t1 t2 t3 LRCLK or LRCCLK LTCLK or LTCCLK Normal Mode ls_ac LRCLK or LRCCLK LTCLK or LTCCLK Inverted Mode ...

Page 112: ...ay from the Rising Edge or Falling Edge of HTCLK to Data Valid on HTPOS HTNEG t6 3 10 ns NOTES 1 T3 mode 2 E3 mode 3 HTCLK is a buffered version of either FTCLK or HRCLK and as such the duty cycle of HTCLK is determined by the source clock 4 In normal mode HRPOS and HRNEG are sampled on the rising edge of HRCLK and HTPOS and HTNEG are updated on the rising edge of HTCLK 5 In inverted mode HRPOS an...

Page 113: ...is a buffered version of either FTCLK or HRCLK and as such the duty cycle of FRCLK is determined by the source clock 4 FTSOF is configured to be an input 5 FTSOF is configured to be an output 6 In normal mode FTD and FTSOF if it is configured as an input is sampled on the rising edge of FTCLK and FRDEN FRD FRSOF and FTDEN and FTSOF if it is configured as an output are updated on the rising edge of...

Page 114: ...0 ns Hold Time from CCS or CRD or CDS Inactive to CD 15 0 Tri State t5 5 20 ns Wait Time from CWR or CDS Active to Latch CD 15 0 t6 65 ns CD 15 0 Setup Time to CWR or CDS Inactive t7 10 ns CD 15 0 Hold Time from CWR or CDS Inactive t8 2 ns CA 7 0 Hold Time from CWR or CRD or CDS Inactive t9 5 ns CRD CWR or CDS Inactive Time t10 75 ns Muxed Address Valid to CALE Falling t11 10 ns 2 Muxed Address Ho...

Page 115: ...re 13 4 Intel Read Cycle Nonmultiplexed Figure 13 5 Intel Write Cycle Nonmultiplexed Address Valid Data Valid CA 7 0 CD 15 0 CWR CCS CRD t1 t2 t3 t4 t5 t9 t10 Address Valid CA 7 0 CD 15 0 CRD CCS CWR t1 t2 t6 t4 t7 t8 t9 t10 ...

Page 116: ...3 6 Motorola Read Cycle Nonmultiplexed Address Valid Data Valid CA 7 0 CD 15 0 CR W CCS CDS t1 t2 t3 t4 t5 t9 t10 Figure 13 7 Motorola Write Cycle Nonmultiplexed Address Valid CA 7 0 CD 15 0 CR W CCS CDS t1 t2 t6 t4 t7 t8 t9 t10 ...

Page 117: ...t14 NOTE t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS WHICHEVER OCCURS FIRST Figure 13 9 Intel Write Cycle Multiplexed CD 15 0 CRD CCS CWR t1 t2 t6 t4 t7 t8 t10 Address Valid CA 7 0 CALE t11 t12 t13 t14 t14 NOTE t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS WHICHEVER OCCURS FIRST ...

Page 118: ...t14 NOTE t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS WHICHEVER OCCURS FIRST Figure 13 11 Motorola Write Cycle Multiplexed CD 15 0 CR W CCS CDS t1 t2 t6 t4 t7 t8 t10 Address Valid CA 7 0 CALE t11 t12 t13 t14 t14 NOTE t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS WHICHEVER OCCURS FIRST ...

Page 119: ...ITS NOTES JTCLK Clock Period t1 1000 ns JTCLK Clock Low Time t2 400 ns JTCLK Clock High Time t3 400 ns JTMS JTDI Setup Time to the Rising Edge of JTCLK t4 50 ns JTMS JTDI Hold Time from the Rising Edge of JTCLK t5 50 ns Delay Time from the Falling Edge of JTCLK to Data Valid on JTDO t6 2 50 ns Figure 13 12 JTAG Test Port Interface AC Timing Diagram JTCLK JTMS JTDI JTDO t4 t5 t6 t1 t2 t3 ...

Page 120: ...gnals VDD 3 3V 5 TA 0 C to 70 C for DS3112 TA 40 C to 85 C for DS3112N See 3 PARAMETER SYMBOL MIN TYP MAX UNITS NOTES RST Low Time t1 1000 ns FRMECU FTMEI High Time t2 50 ns FRMECU FTMEI Low Time t3 1000 ns Figure 13 13 Reset and Manual Error Counter Insert AC Timing Diagram RST t1 FRMECU FTMEI t2 t3 ...

Page 121: ... The T1 E1 framers locate the frame boundaries and concatenate four T1 E1 data streams into one 8 192MHz data stream which is feed into the DS3134 HDLC controller Figure 14 2 shows an example of a dual unchannelized T3 E3 application In this application the multiplexing capability of the DS3112 is disabled and it is only used as a T3 E3 framer Figure 14 1 Channelized T3 E3 Application DS3134 CHATE...

Page 122: ...m 14 2 M13 Basics M13 multiplexing is a two step process of merging 28 T1 lines into a single T3 line First four of the T1 lines are merged into a single T2 rate and then seven T2 rates are merged to form the T3 The first step of this process is called a M12 function since it is merging T1 lines into T2 The second step of this process is called a M23 function since it is merging T2 lines into a T3...

Page 123: ...s a Remote Alarm Indication RAI It will be set to a zero X 0 when the T2 framer cannot synchronize It will be set to a one X 1 otherwise 14 4 M12 Multiplexing The M12 function multiplexes four T1 lines into a single T2 line Since there are four M subframes in the T2 framing structure it might be concluded that each M subframe supports one T1 line but this is not the case The four T1 lines are bit ...

Page 124: ... Block X 48 Info Bits C1 48 Info Bits F1 0 48 Info Bits C2 48 Info Bits C3 48 Info Bits F2 1 48 Info Bits NOTE M1 IS TRANSMITTED AND RECEIVED FIRST Bit 7 Figure 14 4 T2 Stuff Block Structure M1 Subframe F2 Stuff Bit 1 Info Info Bit 3 Info Bit 4 Info Bit 5 Info Bit 6 Info Info Bit 8 Info Bit 48 Bit 2 M2 Subframe F2 Info Bit 1 Stuff Bit 2 Info Bit 3 Info Bit 4 Info Bit 5 Info Bit 6 Info Bit 7 Info B...

Page 125: ...he preceding M frame not including the M F X and C overhead bits P1 and P2 are always the same value if they are not the same value this implies a parity error X Bits X1 X2 The X bit is used as a Remote Alarm Indication RAI It will be set to a zero X1 X2 0 when the T3 framer cannot synchronize or detects AIS It will be set to a one X1 X2 1 otherwise The value of the X bits should not change more t...

Page 126: ...annel contains all ones 2 1 2 3 Unused Unused Unused All unused bits are set to a one 1 3 1 2 3 C Bit Parity CP C Bit Parity CP C Bit Parity CP All three CP bits are set to the same value as the two P bits If the three CP bits are not equal a majority vote is used to decode the true value 4 1 2 3 FEBE FEBE FEBE All three Far End Block Error FEBE bits shall be set to one 111 if the local T3 framer ...

Page 127: ...Bits F4 1 84 Info Bits M4 Subframe Stuff Block P2 84 Info Bits F1 1 84 Info Bits C1 84 Info 84 Info F3 0 F4 Bits F2 0 Info Bits C2 84 Bits 84 Info Bits C3 84 Info Bits 1 84 Info Bits M5 Subframe Stuff Block M1 0 C1 Bits Info 84 Info Bits F1 1 84 Info Bits 84 Info Bits F2 0 84 Info Bits C2 84 Info Bits F3 0 84 Info C3 84 Info Bits F4 1 84 Bits M6 Subframe Stuff Block M2 1 84 Info Bits F1 1 84 Info ...

Page 128: ... 1 Info Bit 2 Info Bit 3 Info Bit 4 Info Bit 5 Stuff Bit 6 Info Bit 7 Info Bit 8 Info Bit 84 M7 Subframe F4 Info Bit 1 Info Bit 2 Info Bit 3 Info Bit 4 Info Bit 5 Info Bit 6 Stuff Bit 7 Info Bit 8 Info Bit 84 14 8 E13 Basics E13 multiplexing is a two step process of merging 16 E1 lines into a single E3 line First four of the E1 lines are merged into a single E2 rate and then four E2 rates are merg...

Page 129: ...g Bit will not be used for tributary data 14 10 Figure 14 8 E3 Framing Structure and E23 Multiplexing The E3 frame structure and the E23 multiplexing scheme are almost identical to the E2 framing structure and the E12 multiplexing scheme The E3 frame structure is made up of four 384 bit sets The four sets are transmitted one after another Set1 Set2 Set3 Set4 Set1 to make up the complete E3 frame s...

Page 130: ...IFICATION CONTROL BITS J TRIBUTARY NUMBER I CONTROL BIT NUMBER NOTE 4 SJ STUFFING BITS J TRIBUTARY NUMBER Figure 14 8 E3 Frame Structure Set 1 Bit 1 Bit 384 FAS 1111010000 RAI Sn b11 b21 b31 b41 b12 bits from the tributaries Set 2 Bit 1 Bit 384 c11 c21 c31 c41 bits from the tributaries Set 3 Bit 1 Bit 384 c12 c22 c32 c42 bits from the tributaries Set 4 Bit 1 Bit 384 c12 c22 c32 c42 s1 s2 s3 s4 bit...

Page 131: ...ke the normal T2 to T3 multiplexing scheme Once the three E1 lines have been multiplexed together the resultant 6 312Mbps data stream is treated just like a T2 data stream that contains four T1 lines We will only discuss the G 747 multiplexing scheme in this section See Section 14 6 for details on the T2 to T3 multiplexing scheme e g M23 and the T3 framing structure Table 14 6 G 747 Carrier Rates ...

Page 132: ... of Sets 3 4 and 5 are the Justification Control Bits Bits 4 to 6 of Set 5 are the Stuffing Bits The Justification Control bits control when data will be stuffed into the Stuffing Bit positions When a majority of the three Justification Control Bits from a particular tributary is set to zero the Stuffing Bit position will be used for tributary data When the Justification Control Bits are majority ...

Page 133: ...ice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products Inc The Dallas logo is a registered trademark of Dallas Semiconductor Corporation 15 1 15 PACKAGE INFORMATION The package drawing s in this data sheet may not reflect the most current specifications The ...

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