7.Electrical Interface
© 2023 China Daheng Group, Inc. Beijing Image Vision Technology Branch 117
When the external input voltage is 5V, there is no need for circuit-limiting resistance in the external
input. But if there is a series resistance, please ensure the value is less than 90Ω. In order to protect
the Line0+ while the external input voltage is higher than 9V, a circuit-limiting resistance is needed in
the external input. The recommended resistance is shown in Table 7-3
External input voltage
Circuit-limiting resistance Rlimit
Line0+ input voltage
5V
Non or <90Ω
About 5V
9V
680Ω
About 5.5V
12V
1kΩ
About 6V
24V
2kΩ
About 10V
Table 7-3 Circuit-limiting resistor value
The connection method of the opto-isolated input circuit and the NPN and PNP photosensor is shown in
Figure 7-2 and Figure 7-3. The relationship between the pull-up resistor value and the external power
supply voltage is shown in Table 7-3.
8
5
1
4
3
7
2
6
3.3V
Line0+
Line0-
FPGA INPUT0
External circuit
Camera internal circuit
Signal
output
Power +
PWR
GND
NPN
Pull-up
resistor
Figure 7-2 NPN photosensor connected to opto-isolated input circuit
8
5
1
4
3
7
2
6
3.3V
Line0+
Line0-
FPGA INPUT0
External
circuit
Camera internal circuit
Signal
output
Power +
PWR
GND
PNP
Current
limiting
resistor
Figure 7-3 PNP photosensor connected to opto-isolated input circuit
Rising edge delay: <50μs (0°C~45°C), parameter description as shown in Figure 7-4
Falling edge delay: <50μs (0°C~45°C), parameter description as shown in Figure 7-4