Daewoo DV-700S, Service Manual

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14
CIRCUIT OPERATIONAL DESCRIPTION
5. SDROM : HY57V641620HGT-H(HY57V641620HGT-55)
This sends and receives data with MPEG decoder and performs the video signal
processing. Every video signal output from DVD player is once stored in SDRAM and
then encoded in MPEG decoder and finally output into the analog signal.
SDRAM applied to DVD module has the capacity of 64MBit(1048576 x 16bit x
4Bank), sends and receives data with MPEG decoder by 16 bit.
Description
The Hynix HY57V641620HGT-H is a 67,108,864-bit CMOS Synchronous DRAM,
ideally suited for the main memory applications which require large memory
density and high bandwidth. HY57V641620HGT-H is organized as 4banks of
1,048,576x16.
HY57V641620HGT-H is offering fully synchronous operation referenced to a
positive edge of the clock. All inputs and outputs are synchro-nized with the
rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with
LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the
number of consecutive read or write cycles initiated by a single control command
(Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or
interleave). A burst of read or write cycles in progress can be terminated by a
burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a
`2N` rule.)