4
(4) PIN DESCRIPTION
Figure 2. Pin Description
RESET
Reset
(input, active low). The ST9+ is initialised
by the Reset signal. With the deactivation of RESET,
program execution begins from the Program memory
location pointed to by the vector contained in program
memory locations 00h and 01h.
R/G/B
Red/Green/Blue.
Video color analog DAC out-
puts
FB
Fast Blanking.
Video analog DAC output.
VOD
Main power supply voltage(5V 10%, digital)
WSCF, WSCR
Analog pins for the VPS/WPP slicer line
PLL.
MCFM
Analog pin for the display pixel frequency multi-
plier.
OSCIN, OSCOUT
Oscillator
(input and output).
These pins connect a parallel-resonant crystal(24MHz
maximum), or an external source to the on-chip clock
oscillator and buffer. OSCIN is the input of the oscilltor
inverter and internal clock generator; OSCOUT is the
output of the oscillator inverter.
VSYNC
Vertical Sync.
Vertical video synchronisation
input to OSD. Positive or negative polarity.
HYNC/CSYNC
Horizontal/Composite sync.
Horizontal
or composite video synchronisation input to OSD. Posi-
tive or negativety.
PXFM
Analog pin for the Display Pixel Frequency Multi-
plier
AVDD
Analog VDD of PLL.
This pin must be tied to
VDD externally to the ST92195.
GND
Digital circuit ground.
AGND
Analog circuit ground(must be tied externally to
digital GND).
CVBS1
Composite video input signal for the Teletext
slicer and sync extraction.
CVBS2
Composite video input signal for the VPS/WSS
slicer. Pin AC coupled.
AVDD1, AVDD2
Analog power supplies(must be tied
externally to AVDD).
TXCF
Analog pin for the VPS/WSS line PLL.
CVBSO, JTDO, JTCK
Test pins : leave floating.
JTMS, TEST0
Test pins : must be tied to AVDD2.
JTRST0
Test pin : must be tied to GND.
IC DESCRIPTION
APPENDIX
Summary of Contents for DTW - 2810F
Page 5: ...4 CIRCUIT BLOCK DIAGRAM ...
Page 6: ...5 ALIGNMENT INSTRUCTIONS User Remocon 1 R 22D05 ...
Page 7: ...6 2 R 23D05 ALIGNMENT INSTRUCTIONS ...
Page 12: ...11 SCHEMATIC DIAGRAM ...
Page 13: ...12 ...
Page 16: ...15 PRINTED CIRCUIT BOARD ...