Daewoo DTU-28A8FZP, Service Manual

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CP-530 Service Manual
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35 PIO5/C8 87 MIU_ADDR[8] 139 WE 191 V
DDC
36 SC0_DA 88 MIU_ADDR[9] 140 CAS 192 V
SSC
37 SC0_CMDVCC 89 MIU_ADDR[10] 141 RAS 193 V
SSP
38 SC0_RST 90 MIU_ADDR[11] 142 SDRAM_ADDR[12] 194 PCST0[0]
39 SC0_OFF 91 MIU_ADDR[12] 143 SDRAM_ADDR[11] 195 PCST1[2]
40 SCO_CCK 92 MIU_ADDR[13] 144 SDRAM_ADDR[9] 196 PCST1[1]
41 V
DDC
93 MIU_ADDR[14] 145 SDRAM_ADDR[8] 197 PCST1[0]
42 V
SSC
94 VDDP 146 SDRAM_ADDR[7] 198 USB_OVRCUR
43 V
DDP
95 VSSP 147 SDRAM_ADDR[6] 199 USB_PWR
44 V
SSP
96 MIU_ADDR[15] 148 SDRAM_ADDR[5] 200 USB_DP
45 PIO6/SC1_DA 97 MIU_ADDR[16] 149 SDRAM_ADDR[4] 201 USB_DM
46
PIO7/SC1_CMDVCC
98 MIU_ADDR[17] 150 SDRAM_ADDR[13] 202 SD_OUT
47
PIO8/SC1_RST
99 MIU_ADDR[18] 151 SDRAM_ADDR[14] 203 SCK_OUT
48
PIO9/SC1_CCK
100 MIU_ADDR[19] 152 SDRAM_ADDR[10] 204 WS_OUT
49
PIO10/SC1_CCK
101 MIU_ADDR[20] 153 SDRAM_ADDR[0] 205 FSCLK
50 MIU_BAA 102 MIU_ADDR[21] 154 SDRAM_ADDR[1] 206 SPDIF
51 MIU_CLK 103 MIU_ADDR[22] 155 SDRAM_ADDR[2] 207 TDO/DSU_TPC0
52 MIU_DATA[15] 104 MIU_ADDR[23] 156 SDRAM_ADDR[3] 208 TDI
4.7.2 Features
General features
·
Targeted to provide a low cost solution for Set Top Box technology
·
Comprehensive driver software and development tool support
·
3.3 V and 1.2V power supplies
·
Philips CMOS 0.12m process technology
·
SQFP208 package
CPU related features
The pnx831x includes an embedded 32-bit MIPS RISC-based CPU which have the following
main features:
·
32-bit PR1910 core operating at 120 MHz.
·
MIPS-II ISA and MIPS16 instruction set
·
Unified 8K Byte Instruction/Data cache
·
4K Byte deeply embedded memory.
·
Two 32-bit timers with compare and enable
·
One 32 -bit watchdog timer with compare and a watchdog interrupt
·
Copy-back store policy, write on allocate
·
Debug Support Unit (DSU) with Enhanced JTAG interface version 2.0
DMA features
Thepnx831x has an integrated 4-channel high performance DMAC ontroller engine that can
Be used to perform a variety of tasks in the system.
·
supports 4 DMA channels allowing transfer from any memory location or peripherals to any
memory location. The arbitration mechanism between the 4 channels is round-robin.