Daewoo DTL- 25G6F, Service Manual

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13
TDA8844N2 (I
2
C-bus controlled PAL/NTSC/SECAM TV Processors)
(1) General Description
The TDA8844N2 is I2C-bus controlled single chip TV processors which are intended to be applied in PAL/NTSC
television receiver.
The IC is mounted in a S-DIP 56 envelope.
(2) Feature
• Video
- Integrated luminance delay line
- Integrated chroma trap and bandpass filters (auto calibrated)
- Asymmetrical peaking circuit in the luminance channel
- Black stretching of non standard CVBS or luminance signals
• RGB
- RGB control circuit with “Continuous Cathode Calibralion” and white point adjustment.
• Input / Output
- Flexible source selection with CVBS switch and Y(CUBS)/C input so that a comb filter can be applied.
- The output signal of the video source select is externally available ( also as CVBS when Y/C input is used).
- External audio input.
- Linear RGB input with fast blanking.
• Synchronization and Deflection
- Horizontal synchronization with two control loops and alignment free horizontal oscillator.
- Slow start and slow stop of the horizontal drive output to enable low stress start-up and switch-off from the line circuit
at nominal line supply voltage.
- Vertical count-down circuit for stable behavior with provisions for non-standard signals.
- Vertical geometry control.
- Vertical drive optimized for DC coupled vertical output stages.
• Control
- Full I2C bus control, as well for customer controls as for factory alignment.
- All automatic controls have an option for forced mode.
• Packaging
- SDIP-56(Soldering Dual in-line Packages)