Daewoo DTK-28 Series, Service Manual, Page: 29 / 71

CP-850/F Service Manual
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IC architecture
A clock generator converts different external line locked clock rates to a common internal sample rate of ~40 MHz, in
order to provide a higher horizontal resolution. The input interface accepts ITU-R 601 at 27 or 32 MHz and ITU-R 656
with encoded or external sync at 54 MHz. The horizontal scaler is used for the scan rate conversion and for the
nonlinear aspect ratio conversion as well.
For the picture improvement, luma and chroma are processed separately. The luminance contrast ratio can be
extended with a dynamic black level expander. In addition the frequency characteristic is improved by a transient
improvement (LTI) and an adaptive dynamic peaking circuit. The peaking adapts to small AC amplitudes of high
frequency parts, while large AC amplitudes are processed by the LTI. The chroma signal is enhanced with a transient
improvement (CTI) with proper limitation to avoid wrong colours. The full programmable RGB matrix covers control of
colour saturation and temperature. A digital white drive control is used to adjust the white balance and for the beam
current limitation to prevent the CRT from over-load. A non-linear colorspace enhancer (NCE) for RGB gives full
flexibility for any amplitude characteristic. High speed10-bit D/A converters are used to convert digital RGB to analog
signals. Separate 9-bit D/A converters control brightness and cutoff. For picture tubes equipped with an appropriate
yoke a scan velocity modulation (SVM) signal is calculated using a differentiated luminance signal.Two analog sources
can be inserted in the main RGB, controlled by separate fastblank (FBL) signals. Contrast and brightness are adjusted
separately from main RGB. One input is dedicated to RGB for on screen display (OSD). The second input is
processed with an analog RGB matrix to insert YCbCr/YpbPr or RGB with control of colour saturation and
programmable half contrast. The bandwidth of ~30MHz guarantees pixel based graphics to be displayed with full
accuracy. All previously mentioned features are implemented in dedicated hardware. An integrated processor controls
the horizontal and vertical deflection, tube measurement loops and beam current limitation. It is also used to calculate
an amplitude histogram of the displayed image.
The horizontal deflection is synchronized with two numeric phase-locked loops (PLL) to the incoming sync. One PLL
generates the horizontal timing signals, e.g. blanking and key-clamping. The second PLL adjusts the phase of the
horizontal drive pulse with a subpixel accuracy less than 1 ns.
Vertical deflection and east/west correction waveforms are calculated as 6th order polynomials. This allows adjustment
of an east/west parabola with trapezoidal, pincushion and an upper/lower corner correction (even for real flat CRT’s),
as well as a vertical sawtooth with linearity and S-correction. Scaling both waveforms, and limiting to fix amplitudes,
performs a vertical zoom or compression of the displayed image. A field and line frequent control loop compensates
picture content depending EHT distortions.