Daewoo DSL-19M1TC, Service Manual

Page: 14 / 62

SVN 204 AI Negative analog sync input for channels 1 through 4.
This acts as the return Path for the Sources connected to SV Channel Inputs. This has to be AC coupled
using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board.
VO_GND 205 AG Analog Ground. Must be directly connected to the analog system ground plane on board.
VOUT2 206 AO Analog VOUT signal
This is the Analog Video Output from the Decoder in the Composite Video format. This can be amplified
and be fed to any video display device.
VDD18_SC 207 AP Analog Power (1.8V) for SYNC Channel. Must be bypassed with 0.1uF capacitor to the analog system
ground plane.
GND18_SC 208 AG Analog Ground (1.8V Return) for SYNC channel. Must be directly connected to the analog system ground
plane on board.
Table 2: Low Bandwidth ADC Input Port
Pin Name No I/O Description
VDDA33_LBADC 1 AP Analog Power (3.3V) for Low Bandwidth ADC Block. Must be bypassed with 0.1uF capacitor.
LBADC_IN1 2 AI Low Bandwidth Analog Input-1. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
LBADC_IN2 3 AI Low Bandwidth Analog Input-2. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
LBADC_IN3 4 AI Low Bandwidth Analog Input-3. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
LBADC_IN4 5 AI Low Bandwidth Analog Input-4. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
LBADC_IN5 6 AI Low Bandwidth Analog Input-5. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
LBADC_IN6 7 AI Low Bandwidth Analog Input-6. The Input signal connected to this Pin, must be bypassed with
LBADC_RTN 8 AG This Pin provides the Return Path for LBADC inputs. Must be directly connected to the analog system
ground plane on board.
VSSA33_LBADC 9 AG Analog Ground for Low Bandwidth ADC Block. Must be directly connected to the analog system ground
plane on board.
Table 3: RCLK PLL Pins
Pin Name No I/O Description
GND_RPLL 11 DG Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane.
VDD_RPLL_18 12 DP Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to Ground Plane.
VBUFC_RPLL 13 O Test Output. Leave this Pin Open. This is reserved for Factory Testing Purpose.
AGND_RPLL 14 AG Analog ground for the Reference DDS PLL. Must be directly connected to the analog system ground
plane.
XTAL 15 AO Crystal oscillator output.
TCLK 16 AI Reference clock (TCLK) from the 14.3MHz crystal oscillator.
AVDD_RPLL_33 17 AP Analog Power (3.3V) for RCLK PLL. Must be bypassed with 0.1uF capacitor.
Table 4: Digital Video Input Port
Pin Name No I/O Description
VID_CLK_1 153 I Video port data clock input meant for Video Input – 1. Up to 75Mhz
[Input, 5V-tolerant]
VIDIN_HS 122 I When Video Input – 1 is in BT656 Mode, this Pin acts as Horizontal Sync Input for Video Input – 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Horizontal Sync Input for Video Input – 1.
OR this Pin acts as Horizontal Sync Input for 24 Bit Video Input
VIDIN_VS 121 I When Video Input – 1 is in BT656 Mode, this Pin acts as Vertical Sync Input for Video Input – 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Vertical Sync Input for Video Input – 1.
OR this Pin acts as Vertical Sync Input for 24 Bit Video Input
VID_DATA_IN_0
VID_DATA_IN_1
VID_DATA_IN_2
VID_DATA_IN_3
VID_DATA_IN_4
VID_DATA_IN_5
VID_DATA_IN_6
VID_DATA_IN_7 135
136
137
138
139
140
141
142 IO Input YUV data in 8-bit BT656 of Video Input – 1
[Bi-Directional, 5V-tolerant]
OR Input Y Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
OR Input Red Data in case of 24 Bit Video Input