Daewoo DDT-21H9ZDF(21") Service Manual Download Page 45

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Service Manual CP-099/FS

The TDA9886 is controlled via the 2-wire I

C-bus by a microprocessor. Two wires serial data(SDA) and serial clock (SCL) carry

information between the devices connected to the bus. The TDA9886 has an I

C-bus slave transceiver with auto-increment.

To avoid conflicts in a real application with other IC's providing similar or complementing functions, there are two
possible slave addresses available which can be selected by pin 12. A slave address is sent from the master to the slave receiver.
The slave address or the ICs given in Table 1. The circuit operates up to clock frequencies of 400 kHz.

The bandgap circuit internally generates a voltage of approximately 2.4 V, independent of supply voltage and temperature.
A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.55 V which is used as an internal reference
voltage.

5-2-15 I

C-bus transceivers and MAD (module address)

Table 1 Slave address

5-2-16 Internal voltage stabilizer

R/W

1/0

The bit A0 is controlled via pin 12. When this pin is connected via a resistor (2.2 k ) to ground, second MAD (A0 = 0) is selected.
if not, first MAD (A0 = 1) is active.
The power-on preset is also dependent on the pin 12 application and can be chosen for NTSC (45.75 MHz) as default or NTSC
(58.75 MHz). By this way the device can be used as NTSC only device without I

C-bus.

5-3 Video - VCT description

5-3-1 Introduction

The VCT 38xxA includes complete video, display, and deflection processing.
All processing is done digitally, the video front-end and video back-end are interfacing to the analogue world.
Most functions can be controlled by software via I 2 C bus slave interface.

5-3-2 Video Front-end

This block provides the analogue interfaces to all video inputs and mainly carries out analogue-to-digital conversion for
the following digital video processing. Most of the functional blocks in the front-end are digitally controlled (clamping,
AGC, and clock-DCO). The control loops are closed by the Fast Processor (‘FP’) embedded in the video decoder

5-3-3 Input Selector

Up to seven analogue inputs can be connected. Four inputs are for input of composite video or S-VHS luma signal.
These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. Two chroma inputs can
be used for connection of S-VHS carrier-chrominance signal. These inputs are internally biased and have a fixed gain
amplifier.

5-3-4 Clamping

The composite video input signals are AC-coupled to the IC. The clamping voltage is stored on the coupling capacitors
and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal.
S-VHS chrominance is also AC-coupled. The input pin is internally biased to the center of the ADC input range. Each
channel is sampled at 10.125 MHz with a resolution of 8 bit.

5-3-5 Automatic Gain Control

A digitally working automatic gain control adjusts the
magnitude of the selected baseband.

5-3-6 Digitally Controlled Clock Oscillator

The clock generation is also a part of the analogue front-end. The crystal oscillator is controlled digitally by the control
processor. The clock frequency can be adjusted within

150 ppm. This adjustment is done in factory for every TV set.

5-3-7 Analogue Video Output

The input signal of the Luma ADC is available at the analogue video output pin (#11). The signal at this pin is buffered
by a source follower. The output voltage is 2 V. The magnitude is adjusted with an AGC in 8 steps together with the
main AGC.