CIRCUIT OPERATIONAL DESCRIPTION
4) SDRAM : AW39S206-7
Description
The AW39S206-7s organlzed as 2-bank x ,048,576-word x 6-bit(2Mx6), fabri-
cated with high performance CMOS technology, Synchronous design allows precise
cycle control with the use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high per-
formance memory system applications.
DQ0
DQ15
UDQM
LDQM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE:
The cell array configuration is 4096 * 256 * 16
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
A0
A9
BS0
BS1
CS
RAS
CAS
WE
A11
SDROM AW39S206-7 Block Diagram
Sm(DAEWOO_DG-K511S)060115.indd 11
2006-1-16 15:30:53
Summary of Contents for DG-K511S
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