Cypress S6J3200 Series, Manual

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CHAPTER 32:Memory Protection Unit for AHB
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1163
2.
Configuration and Block Diagram
This section shows a block diagram of the MPU AHB

Block Diagram of the MPU AHB
Figure 2-1 Block Diagram of MPU AHB

Bus Interface
The bus masters can access the MPU AHB module through its slave bus interface.

Bus Monitor and Protection Logic
This logic monitors the transfers on AHB master interface bus. It finds out the region/s where the current
transfer belongs to and then applies permissions based on the region match. It signals any permission
violation using an NMI interrupt. All transfers on the AHB Master Interface (including the one that caused
permission violation) are blocked until the NMI is cleared.

Control and Status Registers
The operation of the MPU AHB can be controlled and monitored through its Control and Status Registers
(CSR).
AHB AHB memory
AHB master Bus monitor and interface
master protection logic
(before MPU) (after MPU)
AHB bus
NMI
Control and
Status
Registers
MPU
(CSR) stop
Slave bus
interface
Bus interface
Sl
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D
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