S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
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1.4.6 FICR (Flash Interrupt Control Register)
This section explains FICR.
This register is used to enable the interrupt of Flash memory except DualFlash area.
bit
7
6
5
4
3
2
1
0
Field
Reserved
ERRIE
HNGIE
RDYIE
Attribute
RW
RW
RW
Initial value
0
0
0
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2] ERRIE : Flash ECC Error Interrupt Enable
This bit enables ECC error correction interrupt. When ERRIF bit of FISR register is "1" and this bit is "1", an interrupt to
CPU is generated.
Field
bit
Description
ERRIE
2
Flash ECC Error Interrupt Enable
0: ECC error correction interrupt is disabled. (Initial value)
1: ECC error correction interrupt is enabled.
[bit1] HNGIE : Flash HANG Interrupt Enable
This bit enables flash HANG interrupt. When HANGIF bit of FISR register is "1" and this bit is "1", an interrupt to CPU is
generated.
Field
bit
Description
HNGIE
1
Flash HANG Interrupt Enable
0: Flash HANG interrupt is disabled. (Initial value)
1: Flash HANG interrupt is enabled.
[bit0] RDYIE : Flash RDY Interrupt Enable
This bit enables Flash RDY interrupt. When RDYIF bit of FISR register is "1" and this bit is "1", an interrupt to CPU is
generated.
Field
bit
Description
RDYIE
0
Flash RDY Interrupt Enable
0: Flash RDY interrupt is disabled. (Initial value)
1: Flash RDY interrupt is enabled.
