Cypress S29VS128R, Manual

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Document Number: 002-00833 Rev. *L Page 4 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
2. Input/Output Descriptions and Logic Symbol
Table 1 identifies the input and output package connections provided on the device.
Table 1. Input/Output Descriptions
Symbol Type Description
Amax – A16
Higher order address lines. Amax = A23 for VS256R, A22 for VS128R.
On the XS256R and XS128R, these inputs can be left unconnected in AADM mode.
A/DQ15 – A/DQ0 I/O Multiplexed Address/Data input/output
CE# Input Flash Chip Enable. Asynchronous relative to CLK.
OE# Input Output Enable. Asynchronous relative to CLK for the Burst mode.
WE# Input Write Enable
V
CC
Supply Device Power Supply
V
CCQ
Supply Input/Output Power Supply (must be ramped simultaneously with V
CC
)
V
SS
I/O Ground
V
SSQ
I/O Input/Output Ground
NC No Connect No Connected internally
RDY Output Ready. Indicates when valid burst data is ready to be read
CLK Input
The first rising edge of CLK in conjunction with AVD# low latches address input and activates
burst mode operation. After the initial word is output, subsequent rising edges of CLK increment
the internal address counter. CLK should remain low during asynchronous access
AVD# Input
Address Valid input. Indicates to device that the valid address is present on the address inputs
(address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only).
V
IL
= for asynchronous mode, indicates valid address; for burst mode, cause staring address to
be latched on rising edge of CLK.
V
IH
= device ignores address inputs
RESET# Input Hardware Reset. Low = device resets and returns to reading array data.
V
PP
Input
Accelerated input.
At V
HH
, accelerates programming; automatically places device in unlock bypass mode.
At V
IL
, disables all program and erase functions.
Should be at V
IH
for all other conditions.
RFU Reserved Reserved for future use