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Cypress S29GL01GP Manual Download Page 12

Document Number: 002-00886 Rev. *B

Page 12 of 83

S29GL01GP

S29GL512P
S29GL256P
S29GL128P

5.

Additional Resources

Visit 

www.cypress.com

 to obtain the following related documents:

5.1

Application Notes

The following is a list of application notes related to this product. All Cypress application notes are available at 

http://

www.cypress.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx

Using the Operation Status Bits in AMD Devices

Understanding Page Mode Flash Memory Devices

MirrorBit

®

 Flash Memory Write Buffer Programming and Page Buffer Read

Common Flash Interface Version 1.4 Vendor Specific Extensions

MirrorBit

®

 Flash Memory Write Buffer Programming and Page Buffer Read

Taking Advantage of Page Mode Read on the MCF5407 Coldfire

Migration to S29GL128N and S29GL256N based on 110nm MirrorBit

®

 Technology

Optimizing Program/Erase Times

Practical Guide to Endurance and Data Retention

Configuring FPGAs using Cypress S29GL-N Flash

Connecting Cypress™ Flash Memory to a System Address Bus

Connecting Unused Data Lines of MirrorBit

®

 Flash

Reset Voltage and Timing Requirements for MirrorBit

®

 Flash

Versatile IO: DQ and Enhanced

5.2

Specification Bulletins

Contact your local sales office for details.

5.3

Hardware and Software Support

Downloads and related information on Flash device support is available at 

http://www.cypress.com/Support/Pages/DriversSoftware.aspx

Cypress low-level drivers

Enhanced Flash drivers

Flash file system

Downloads and related information on simulation modeling and CAD modeling support is available at

http://www.cypress.com/Support/Pages/SimulationModels.aspx

VHDL and Verilog

IBIS

ORCAD

5.4

Contacting Cypress

Obtain the latest list of company locations and contact information on our web site at 

http://www.cypress.com/About/Pages/Locations.aspx

Summary of Contents for S29GL01GP

Page 1: ...by the customer Uniform 64 Kword 128 Kbyte Sector Architecture S29GL01GP One thousand twenty four sectors S29GL512P Five hundred twelve sectors S29GL256P Two hundred fifty six sectors S29GL128P One hu...

Page 2: ...alues Random Access Read f 5 MHz 30 mA 8 Word Page Read f 10 MHz 1 mA Program Erase 50 mA Standby 1 A Program Erase Times typical values Single Word Programming 60 s Effective Write Buffer Programming...

Page 3: ...mmand Sequences 36 8 Advanced Sector Protection Unprotection 38 8 1 Lock Register 39 8 2 Persistent Protection Bits 39 8 3 Persistent Protection Bit Lock Bit 41 8 4 Password Protection Method 41 8 5 A...

Page 4: ...sector protected 02 VIO VCC 2 7 to 3 6 V lowest address sector protected V1 VIO 1 65 to VCC VCC 2 7 to 3 6 V highest address sector protected V2 VIO 1 65 to VCC VCC 2 7 to 3 6 V lowest address sector...

Page 5: ...re range I Industrial 40 C to 85 C C Commercial 0 C to 85 C 5 Type 0 is standard Specify other options as required S29GL P Valid Combinations Base Part Number Speed Package 2 3 Temperature 4 Model Num...

Page 6: ...nect Not connected internally RY BY Output Ready Busy Indicates whether an Embedded Algorithm is in progress or complete At VIL the device is actively erasing or programming At High Z the device is in...

Page 7: ...ut Buffers X Decoder Y Decoder Chip Enable Output Enable Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Register VCC VSS VIO WE WP ACC BYTE CE OE STB STB DQ15 D...

Page 8: ...GA packages Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods The package and or data integrity may be compromised if the package body is exposed to tempera...

Page 9: ...ACEMENT NONE DEPOPULATED SOLDER BALLS NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL POSITION DESIGNATION PER JESD 95 1 SPP 010 EXCEPT AS NOTED 4...

Page 10: ...22 A23 A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP ACC RY BY A18 A17 A7 A6 A5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 A24 A25 A16 BYTE VSS DQ15 A 1 DQ7 DQ14 DQ...

Page 11: ...OLD PROTRUSION ALLOWABLE MOLD PROTUSION IS 0 15 mm PER SIDE 5 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0 08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL C...

Page 12: ...10nm MirrorBit Technology Optimizing Program Erase Times Practical Guide to Endurance and Data Retention Configuring FPGAs using Cypress S29GL N Flash Connecting Cypress Flash Memory to a System Addre...

Page 13: ...evice on a single page Sectors and their address ranges that are not explicitly listed such as SA001 SA1022 have sector starting and ending addresses that form the same pattern as all other sectors of...

Page 14: ...e the pattern xxx0000h xxxFFFFh Note This table has been condensed to show sector related information for an entire device on a single page Sectors and their address ranges that are not explicitly lis...

Page 15: ...array data mode 7 1 Device Operation Table The device must be setup appropriately for each operation Table describes the required state of each control pin for any particular operation Legend L Logic...

Page 16: ...arrive with the address on its inputs The device defaults to reading array data after device power up or hardware reset To read data from the memory array the system must first assert a valid address...

Page 17: ...ge on A9 the host system must issue the Autoselect command The Autoselect command sequence may be written to an address within a sector that is either in the read or erase suspend read mode The Autose...

Page 18: ...GL256P Cycle 1 L L H X X VID X L X L L H 22 X 7Eh Cycle 2 H H L 22 X 22h Cycle 3 H H H 22 X 01h Device ID S29GL128P Cycle 1 L L H X X VID X L X L L H 22 X 7Eh Cycle 2 H H L 22 X 21h Cycle 3 H H H 22 X...

Page 19: ...command multiple reads can be performed after entry manuf_id UINT16 base_addr 0x000 read manuf id Autoselect exit UINT16 base_addr 0x000 0x00F0 exit autoselect write reset command Device ID Word 3 Bas...

Page 20: ...hould be reinitiated once the device has returned to the read mode to ensure data integrity Programming is allowed in any sequence and across sector boundaries for single word programming operation Se...

Page 21: ...2AAh 0055h Program Setup Write Base AAAh Base 555h 00A0h Program Write Byte Address Word Address Data Write Unlock Cycles Address 555h Data AAh Address 2AAh Data 55h Write Program Command Address 555...

Page 22: ...After writing the Starting Address Data pair the system then writes the remaining address data pairs into the write buffer Note that if a Write Buffer address location is loaded multiple times the ad...

Page 23: ...in one operation must be within the same flash page A flash page begins at addresses evenly divisible by 0x20 UINT16 src source_of_data address of source data UINT16 dst destination_of_data flash dest...

Page 24: ...ddress SA wc Unlock Cycle 1 Unlock Cycle 2 wc number of words 1 Yes Yes Yes Yes Yes No No No No No wc 0 Write Buffer Abort Desired Write Buffer Abort Polling Status Done Error FAIL Issue reset command...

Page 25: ...se status bits Once the sector erase operation has begun only the Erase Suspend command is valid All other commands are ignored However note that a hardware reset immediately terminates the erase oper...

Page 26: ...eturn to reading array PASS Device returns to reading array Perform Write Operation Status Algorithm Select Additional Sectors Unlock Cycle 1 Unlock Cycle 2 Yes Yes Yes Yes Yes No No No No Last Sector...

Page 27: ...details on the Unlock Bypass function Any commands written during the chip erase operation are ignored However note that a hardware reset immediately terminates the erase operation If that occurs the...

Page 28: ...omplete the device returns to the erase suspend read mode The system can determine the status of the program operation using write operation status bits just as in the standard program operation In th...

Page 29: ...operation See Autoselect on page 17 for more information After the Program Resume command is written the device reverts to programming The system can determine the status of the program operation usin...

Page 30: ...nstead of the normal four cycles This mode dispenses with the initial two unlock cycles required in the standard program command sequence resulting in faster total programming time The Command Definit...

Page 31: ...g Erase Suspend When the Embedded Program algorithm is complete the device outputs the datum programmed to DQ7 The system must provide the program address to read valid status information on DQ7 If a...

Page 32: ...n DQ6 DQ0 may be still invalid Valid data on DQ7 D00 appears on successive read cycles See the following for more information Table shows the outputs for Data Polling on DQ7 Figure 7 4 shows the Data...

Page 33: ...erasing or is erase suspended DQ6 by comparison indicates whether the device is actively erasing or is in Erase Suspend but cannot distinguish which sectors are selected for erasure Thus both status b...

Page 34: ...command If additional sectors are selected for erasure the entire time out also applies after each additional sector erase command When the time out period is complete DQ3 switches from a 0 to a 1 If...

Page 35: ...rain output several RY BY pins can be tied together in parallel with a pull up resistor to VCC This feature allows the host system to detect when data is ready to be read by simply monitoring the RY B...

Page 36: ...ts the sectors to the read and address bits are ignored Reset commands are ignored during program and erase operations The reset command may be written between the cycles in a program command sequence...

Page 37: ...istent Method DQ1 Lock Register One Time Programmable PPB Lock Bit 1 2 3 64 bit Password One Time Protect 1 PPBs Unlocked 0 PPBs Locked Memory Array Sector 0 Sector 1 Sector 2 Sector N 2 Sector N 1 Se...

Page 38: ...three states 1 Constantly locked The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password hardware reset or power cycle 2 Dynamically locked The sel...

Page 39: ...state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 8 2 Figure 8 2 PPB Program Algorithm Read Byte Twi...

Page 40: ...perates normally again 6 To achieve the best protection it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP ACC VIL Note that the P...

Page 41: ...password programming operation 13 All further commands to the password region are disabled and all operations are ignored 14 If the password is lost after setting the Password Mode Lock Bit there is n...

Page 42: ...XXXh Data A0h Address XXXh Data PD Unlock Cycle 1 Unlock Cycle 2 XXXh Address don t care Program Data PD See text for Lock Register definitions Caution Lock register can only be progammed once PASS Wr...

Page 43: ...ed Sector Protection Unprotection on page 38 If the system asserts VIH on the WP ACC pin the device reverts to whether the boot sectors were last set to be protected or unprotected That is sector prot...

Page 44: ...les this mode when addresses remain stable for tACC 30 ns The automatic sleep mode is independent of the CE WE and OE control signals Standard address access timings provide new data when addresses ar...

Page 45: ...Erase algorithm The ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled 10 1 Factory Locked Secured Silicon Sector The Factory Locked Secured Silicon Sec...

Page 46: ...the Secured Silicon Sector region until the system issues the four cycle Exit Secured Silicon Sector command sequence See Command Definitions on page 64 Secured Silicon Sector Command Table Appendix T...

Page 47: ...e 2 UINT16 base_addr 0x555 0x0090 write SecSi Sector Exit cycle 3 UINT16 base_addr 0x000 0x0000 write SecSi Sector Exit cycle 4 Secured Silicon Sector Program LLD Function lld_ProgramCmd Cycle Operati...

Page 48: ...a time Duration of the short circuit should not be greater than one second 4 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating...

Page 49: ...Figure 11 3 Test Setup Note If VIO VCC the reference level is 0 5 VIO Specifications Range Ambient Temperature TA Industrial I Device 40 C to 85 C Ambient Temperature TA Commercial C Device 0 C to 85...

Page 50: ...1 4 Input Waveforms and Measurement Levels Note If VIO VCC the input measurement reference level is 0 5 VIO Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don t Care Any Chan...

Page 51: ...Hz 6 20 mA CE VIL OE VIH VCC VCCmax f 5 MHz 30 55 CE VIL OE VIH VCC VCCmax f 10 MHz 60 110 IIO2 VIO Non Active Output CE VIL OE VIH 0 2 10 mA ICC2 VCC Intra Page Read Current 1 CE VIL OE VIH VCC VCCma...

Page 52: ...e VIO VCC 2 7 V Min 100 110 120 ns VIO 1 65 V to VCC VCC 3 V 110 120 130 VIO VCC 3 0 V 90 100 110 tAVQV tACC Address to Output Delay 1 VIO VCC 2 7 V Max 100 110 120 ns VIO 1 65 V to VCC VCC 3 V 110 12...

Page 53: ...fic to a read cycle following a flash write operation Figure 11 6 Page Read Timings Note Figure 11 6 shows word mode Addresses are A2 A 1 for byte mode tOH tCE Outputs WE Addresses CE OE HIGH Z Output...

Page 54: ...ing Embedded Algorithms to Read Mode or Write mode Min 35 s tReady RESET Pin Low NOT During Embedded Algorithms to Read Mode or Write mode Min 35 s tRP RESET Pulse Width Min 35 s tRH Reset High Time B...

Page 55: ...eration returns FFh A hardware reset is required 4 VCC maximum power up current RST VIL is 20 mA Figure 11 8 Power up Sequence Timings Power up Sequence Timings Parameter Description Speed Unit tVCS R...

Page 56: ...ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE or OE high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 30 ns tWHDX tDH Data Hold Time Min 0 ns tCEPH CE Hi...

Page 57: ...stration shows device in word mode Figure 11 10 Accelerated Program Timing Diagram Notes 1 Not 100 tested 2 CE OE VIL 3 OE VIL 4 See Figure 11 3 and Table for test specifications OE WE CE VCC Data Add...

Page 58: ...the word mode Figure 11 12 Data Polling Timings During Embedded Algorithms OE CE Addresses VCC WE Data 2AAh SA tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH I...

Page 59: ...stration shows first two status cycle after command sequence last status read cycle and array data read cycle CE does not need to go high between status bit reads Figure 11 14 DQ2 vs DQ6 Note DQ2 togg...

Page 60: ...e to OE low during toggle bit polling Min 15 ns tELAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE or OE high during toggle bit polling Min 0 ns tDVEH tDS Data Setup Time Min 30 ns t...

Page 61: ...ress SA sector address PD program data 3 DQ7 is the complement of the data written to the device DOUT is the data written to the device 4 Waveforms are for the word mode tGHEL tWS OE CE WE RESET tDS D...

Page 62: ...itance Notes 1 Sampled not 100 tested 2 Test conditions TA 25 C f 100 MHz Erase And Programming Performance Parameter Typ Note 1 Max Note 2 Unit Comments Sector Erase Time 0 5 3 5 sec Excludes 00h pro...

Page 63: ...ion 5 For the latest information explore the Cypress web site at www cypress com 12 1 Command Definitions Writing specific address and data commands or sequences into the command register initiates de...

Page 64: ...4 555 AA 2AA 55 555 90 X03 11 CFI Query 12 1 55 98 Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer 13 6 555 AA 2AA 55 SA 25 SA WC WBL PD WBL PD Program Buffer to Flash Confirm 1 SA 29 Write to Bu...

Page 65: ...Table on page 18 for device ID values and definitions 9 The fourth fifth and sixth cycles of the autoselect command sequence are read cycles 10 The data is 00h for an unprotected sector and 01h for a...

Page 66: ...d Read 10 4 00 PWD 0 01 PWD 1 02 PWD 2 03 PWD 3 Password Unlock 10 7 00 25 00 03 00 PWD 0 01 PWD 1 02 PWD 2 03 PWD 3 00 29 Command Set Exit 7 8 2 XXX 90 XXX 00 Global Non Volatile PPB Command Set Entr...

Page 67: ...time programmable Program state 0 and the erase state 1 The Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bit...

Page 68: ...4 AAA AA 555 55 AAA 90 X06 11 CFI Query 12 1 AA 98 Program 4 AAA AA 555 55 AAA A0 PA PD Write to Buffer 13 6 AAA AA 555 55 SA 25 SA WC WBL PD WB L PD Program Buffer to Flash confirm 1 SA 29 Write to...

Page 69: ...Table on page 18 for device ID values and definitions 9 The fourth fifth and sixth cycles of the autoselect command sequence are read cycles 10 The data is 00h for an unprotected sector and 01h for a...

Page 70: ...0 01 PWD 1 02 PWD 2 03 PWD 3 04 PWD 4 05 PWD 5 06 PWD 6 07 PWD 7 Password Unlock 10 11 00 25 00 03 00 PWD 0 01 PWD 1 02 PWD 2 03 PWD 3 04 PWD 4 05 PWD 5 06 PWD 6 07 PWD 7 00 29 Command Set Exit 7 8 2...

Page 71: ...time programmable Program state 0 and the erase state 1 The Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bit...

Page 72: ...vice is in the autoselect mode The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables The system must write the reset command to return the device to re...

Page 73: ...Eh 0006h Typical timeout per single byte word write 2N s 20h 40h 0006h Typical timeout for buffer write 2N s 00h not supported 21h 42h 0009h Typical timeout per individual block erase 2N ms 22h 44h 00...

Page 74: ...s within device 01h uniform device 02h boot device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 00xxh 000xh 0000h 000xh Erase Block Region 1 Information refer to the CFI specification or CFI publication 100 00FFh...

Page 75: ...t 0 Not Supported X Number of sectors in per group 48h 90h 0000h Sector Temporary Unprotect 00 Not Supported 01 Supported 49h 92h 0008h Sector Protect Unprotect scheme 0008h Advanced Sector Protection...

Page 76: ...not be less than tRPH Figure 13 1 Power Up Reset Timing Note The sum of tRP and tRH must be equal to or greater than tRPH Power On and Warm Reset Timing Requirements Parameter Description Type GL P GL...

Page 77: ...sooner than tVCS after VCC exceeds VCC_min and VIO exceeds VIO_min CE or OE must be High at least tCEH 20 ns prior to CE or OE falling edge which initiates the first access CE is ignored during Warm R...

Page 78: ...Sector Erase Write Buffer Programming Operation Sector Erase Operation figures Deleted Wait 4 ms box from flowcharts Password Protection Method Lock Register Program Algorithm figure Deleted Wait 4 ms...

Page 79: ...and Power up Sequence Changed timing specs and waveforms 11 28 2007 A8 Ordering Information New commercial operating temperature option Operating Ranges New operating temperature range 02 15 2008 A9 E...

Page 80: ...and unlock bypass Chip Erase as valid commands Changed paragraph third sentence to sector address of exit command is don t care Writing Commands Command Sequence Changed tables listed in fourth senten...

Page 81: ...dated speed options for S29GL512P Read Operation Timing Figure Added note 10 22 2012 A14 Sector Erase Clarified tSEA Erase Suspend Clarified tSEA Writing Commands Command Sequences Sub section RY BY C...

Page 82: ...plicable law Cypress reserves the right to make changes to this document without further notice Cypress does not assume any liability arising out of the application or use of any product or circuit de...

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