Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 93 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 93
TrueTouch Module
11.2.2 CS_CR1 Register
The TrueTouch Control Register 1 (CS_CR1) contains addi-
tional TrueTouch system control options. Never write to this
register while the block is enabled.
Bit 7: CHAIN. When this bit is a ‘0’, the two 8-bit counters
operate independently. When this bit is a ‘1’, the counters
are chained to operate as a 16-bit counter.
Bits 6 and 5: CLKSEL[1:0].
These bits select the True-
Touch module frequency of operation according to the fol-
lowing table:
Bit 4: RLOCLK. When this bit is a ‘0’, the entire TrueTouch
system runs at the frequency specified in the CLKSEL[1:0]
bits. When this bit is a ‘1’, the High Counter is clocked inde-
pendently by the TrueTouch RLO clock.
Bit 3: INV. Input Invert. When this bit is a ‘0’, the input
polarity is unchanged. When this bit is a ‘1’, the data input
select is inverted.
Bits 2 to 0: INSEL[2:0]. Input Selection. These bits control
the selection of input signals for event control according to
the following table:
For additional information, refer to the CS_CR1 register on
page 212 .
11.2.3 CS_CR2 Register
The TrueTouch Control Register 2 (CS_CR2) contains addi-
tional TrueTouch system control options.
Bits 7 and 6: IRANGE. These bits scale the IDAC current
output.
Bit 5: IDACDIR. This bit determines whether the IDAC
sinks or sources current to the analog global bus when
enabled.
Bit 4: IDAC_EN. This bit enables manual connection of the
IDAC to the analog global bus.
Bit 3: CIN_EN.
This bit enables the negative charge inte-
gration capacitor sense approach. This causes the selected
sense pin to alternately connect to the analog global bus
and ground, at the rate selected by the CLKSEL bits in the
CS_CR1 register.
Bit 2: PXD_EN. This bit drives a clock to each I/O pin that
is enabled for connection to the analog global bus. This
clock alternately connects the pin to the bus, then connects
the pin to ground. The clock rate is selected by the CLKSEL
bits in the CS_CR1 register. In addition, the IDAC sources
current to the bus. The programmable timer is clocked by
this same clock.
Bit 1: CIP_EN. This bit enables the positive charge integra-
tion capacitor sense approach. This causes the reference
buffer and the selected integration capacitor pin(s) to alter-
nately connect to the analog global bus at the rate selected
by the CLKSEL bits in the CS_CR1 register.
Bit 0: RO_EN. This bit enables the relaxation oscillator.
The internal RO is connected to the analog global bus, and
the capacitance of any connected pins affects the RO fre-
quency. The oscillator current is set by the value of the
IDAC_D register.
For additional information, refer to the CS_CR2 register on
page 213 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,A1h CS_CR1 CHAIN CLKSEL[1:0] RLOCLK INV INSEL[2:0] RW : 00
CLKSEL[1:0] Frequency of Operation
00 IMO
01 IMO/2
10 IMO/4
11 IMO/8
INSEL[1:0] Selected Input
000 Comparator 0
001 ILO
010 Comparator 1
011 RLO Timer Terminal Count
100 Internal Timer
101 RLO Timer IRQ
110 Analog Global Mux Bus
111 ‘0’
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,A2h CS_CR2 IRANGE IDACDIR IDAC_EN CIN_EN PXD_EN CIP_EN RO_EN RW : 00
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