Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 89 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 89
TrueTouch Module
Figure 11-10. Negative Charge Integration Block Diagram
The initialization phase for negative CI (charge integration)
is the same as for successive approximation (
Figure 11-7 ).
Following that, a two-phase sequence discharges the inte-
gration capacitor, as illustrated in
Figure 11-11 and
Figure 11-12 .
Figure 11-11. Negative Charge Integration First Phase:
Grounding the Sense Capacitor
Figure 11-12. Negative Charge Integration Second Phase:
Integrating Charge onto Integration Capacitor
11.1.1.5 Sigma Delta
The sigma delta capacitive sensing operates by holding an
integration capacitor voltage near a target threshold, and
charging the voltage up or down based on the present state
of a comparator output. The sense capacitor is continuously
switched between ground and the integration capacitor,
which drives the integrated voltage down on each switching
cycle. When the integration voltage is below the reference
threshold, a current from the internal IDAC is used to charge
the capacitor above the threshold again. The TrueTouch
Sigma Delta (CSD) User Module in PSoC Designer uses
this method.
As the integration capacitor voltage moves back and forth
across the comparator threshold, the comparator "high" out-
puts are counted in an interval to give a measure of the
sense capacitor. The larger the sense capacitor, the more
time the comparator is low, and so the count is less.
To reduce noise, the sense capacitor is driven with a
pseudo-random sequence (PRS). An 8- or 12-bit sequence
can be selected, and the PRS is clocked from a prescaler
giving input rates of the main system clock or any divide-by-
two of this, down to SYSCLK/256. The counter accumulates
counts for a selected interval, typically the cycle length of
the PRS (511 or 1023 cycles of the PRS prescale clock).
When bit 0 (EN) and bit 3 (CSD_MODE) of the CS_CR0
register are set to ‘1’, the TrueTouch counters are enabled to
work in CSD mode. When both CMP0 (this input is double
synchronized) and the "START" signal from Programmable
Timer are ‘1’, the counters increment. When this comparator
output is low, the counters hold their count until the compar-
ator goes high again. In this case:
Reference
Buffer
Vr
s
An
alo
g
Gl
oba
l B
us
TrueTouch Logic
Comparator
Mux
Mux
Refs
TrueTouch
Clock Select
CSCLK and Pin Enables
REF_EN
IMO
CSCLK
Closed
16-Bit Counter
C
EXTERNAL
P0[1] or
P0[3]
CS1
CS2
CSN
Reference
Buffer
Vr
CS1
CS2
CSN
A
n
alog
G
lo
bal
B
u
s
Comparator
Mux
Mux
Vref
Grounded
Open
Closed
C
EXTERNAL
C
INTERNAL
Reference
Buffer
Vr
CS1
CS2
CSN
A
nal
og G
lobal
B
u
s
Com parator
Mux
Mux
Vref
Closed
Closed
Open
C
EXTERNA
C
INTERNAL
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