Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 85
11. TrueTouch Module
This chapter presents the TrueTouch Module and its associated registers. For a quick reference of all PSoC registers in
address order, refer to the
Register Reference chapter on page 187 .
11.1 Architectural Description
11.1.1 Types of TrueTouch Approaches
A block diagram of the overall capacitive sensing architec-
ture is shown in
Figure 11-1 . CS1 through CSN are the
capacitors being measured. The various sensing
approaches use different subsets of this hardware.
Figure 11-1. TrueTouch Module Block Diagram
11.1.1.1 Positive Charge Integration
In the positive charge integration method, charge on a
sense capacitor is integrated onto a larger capacitor, starting
from ground. The number of cycles required to reach a tar-
get voltage gives a measurement of the sensed capaci-
tance. The hardware configuration for this approach is
shown in
Figure 11-2 . The hardware supports the use of
either pin P0[1] or P0[3] for the external integration capaci-
tor.
Figure 11-2. Positive Charge Integration Block Diagram
IDAC
Reference
Buffer
Vr
C
EXTERNAL
C
INTERNAL
Analog G
lo
ba
l B
u
s
TrueTouch Counters
Comparator
Mux
Mux
Refs
Relaxation
Oscillator (RO)
CSCLK
IMO
+
-
TrueTouch
Clock Select
CS1
CS2
CSN
Reference
Buffer
Vr
An
al
og
G
lo
bal
Bu
s
TrueTouch Logic
Comparator
Mux
Mux
Refs
TrueTouch
Clock Select
Pin Enables
CSCLK
CSCLK
IMO
CSCLK
16-Bit Counter
C
EXTERNAL
P0[1] or
P0[3]
s
CS1
CS2
CSN
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