Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 80 / 308

80 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Sleep and Watchdog
10.4.2 Wakeup Sequence
After asleep, the only event that wakes the system is an
interrupt. The Global Interrupt Enable of the CPU Flag regis-
ter does not need to be set. Any unmasked interrupt wakes
the system up. It is optional for the CPU to actually take the
interrupt after the wakeup sequence.
The wakeup sequence is synchronized to the taps from the
wakeup timer (running on IMO clock). This allows the Flash
memory module enough time to power up before the CPU
asserts the first read access. Another reason for the delay is
to allow the IMO, bandgap, and LVD/POR circuits time to
settle before actually being used in the system. As shown in
Figure 10-2 , the wakeup sequence is as follows.
1. The wakeup interrupt occurs and the sequence is initi-
ated at INT (shown in Figure 10-2 on page 75 ). The
interrupt asynchronously enables the regulator, the
bandgap circuit, LSO, POR, and the IMO. As the core
power ramps, the IMO starts to oscillate and the remain-
der of the sequence is timed with configurable durations
from the wakeup timer.
2. At T1, the bandgap is sampled and the Flash is enabled.
3. At T2, the Flash is put in power saving mode (idle).
4. At T3, the POR/LVD comparators are sampled and the
CPU restarts.
There is no difference in wakeup from deep sleep or buzzed
sleep because in all cases, in order to achieve the power
specification, the regulator, references and core blocks must
be shut off.
10.4.3 Bandgap Refresh
During normal operation the bandgap circuit provides a volt-
age reference (VRef) to the system for use in the analog
blocks, Flash, and
low voltage detect (LVD) circuitry. Nor-
mally, the bandgap output is connected directly to the VRef
signal. However, during sleep, the
bandgap reference
gen-
erator block and LVD circuits are completely powered down.
The bandgap and LVD blocks are periodically reenabled
during sleep to monitor for low voltage conditions. This is
accomplished by periodically turning on the bandgap.
The rate at which the refresh occurs is related to the 32 kHz
clock and controlled by the Power System Sleep Duty Cycle.
Table 10-1 lists the available selections.
Figure 10-4. Buzz Sequence Timing
The buzz sequence after the Buzz signal comes. This is shown in Figure 10-4, “Buzz Sequence Timing,” on page 80 .
Table 10-1. Power System Sleep Duty Cycle Selections
PSSDC Sleep Timer Counts Period (Nominal)
00b (default) 256 8 ms
01b 1024 31.2 ms
10b 64 2 ms
11b 16 500 µs
Note Valid when ALT_Buzz[1:0] of the SLP_CFG2 register is 00b.
P o w e r g o o d
B U Z Z
R e g u la to r E n a b le
r s w itc h e s E n a b le
B a n d g a p E n a b le
P O R E n a b le
IM O E n a b le
T 0 T 1 T 2 T 3
B U Z Z
S a m p le B a n d g a p
S w itc h re fe re n c e
o m s ta n d b y to B G
S a m p le P O R
T 4
2 IM O
c y c le s
1 0 -3 0 u s 3 -1 0 u s
1 -1 0 u s
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