Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 76 / 308

76 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Sleep and Watchdog
Note The T0, T1, and T2 mentioned in the SLP_CFG3 reg-
ister with respect to Figure 10-2 on page 75 are defined as
follows:
■
T0: Time duration between T0 and T1 in the timing dia-
gram.
■
T1: Time duration between T1 and T2 in the timing dia-
gram.
■
T2: Time duration between T3 and T4 in the timing dia-
gram.
10.1.2 Sleep Timer
The Sleep Timer is a 15-bit up counter clocked by the 32
kHz clock source. This timer is always enabled except in
deep sleep mode. The exception to this is within an
ICE ( in-
circuit emulator ) in debugger mode and when the Stop bit
in the CPU_SCR0 is set; the sleep timer is disabled, so that
the user does not get continual watchdog resets when a
breakpoint is hit in the debugger environment.
If the associated sleep timer interrupt is enabled, a periodic
interrupt to the CPU is generated based upon the sleep
interval selected from the OSC_CR0 register. The sleep
timer functionality does not need to directly associate with
the sleep state. It can be used as a general purpose timer
interrupt regardless of sleep state.
The reset state of the sleep timer is a count value of all
zeros. There are two ways to reset the sleep timer. Any
hardware reset, (that is, POR, XRES, or Watchdog Reset
(WDR)) resets the sleep timer. There is also a method that
allows the user to reset the sleep timer in firmware. A write
of 38h to the RES_WDT register clears the sleep timer.
Note Any write to the RES_WDT register also clears the
watchdog timer.
Clearing the sleep timer is done at anytime to synchronize
the sleep timer operation to CPU processing. A good exam-
ple of this is after POR. The CPU hold off, due to voltage
ramp and others, may be significant. In addition, a signifi-
cant amount of program initialization may be required. How-
ever, the sleep timer starts counting immediately after POR
and is at an arbitrary count when user code begins execu-
tion. In this case, it is desirable to clear the sleep timer
before enabling the sleep interrupt initially to ensure that the
first sleep period is a full interval.
10.2 Application Overview
The following are notes regarding sleep related to firmware
and application issues.
Note 1 If an interrupt is pending, enabled, and scheduled to
be taken at the instruction boundary after the write to the
SLEEP bit, the system does not go to sleep. The instruction
still executes, but it cannot set the SLEEP bit in the
CPU_SCR0 register. Instead, the interrupt is taken and the
effect of the sleep instruction ignored.
Note 2 There is no need to enable the Global Interrupt
Enable (CPU_F register) to wake the system out of sleep
state. Individual interrupt enables, as set in the interrupt
mask registers, are sufficient. If the Global Interrupt Enable
is not set, the CPU does not service the ISR associated with
that interrupt. However, the system wakes up and continues
executing instructions from the point at which it went to
sleep. In this case, the user must manually clear the pending
interrupt or subsequently enable the Global Interrupt Enable
bit and let the CPU take the ISR. If a pending interrupt is not
cleared, it is continuously asserted. Although the SLEEP bit
may be written and the sleep sequence executed as soon as
the device enters sleep mode, the SLEEP bit is cleared by
the pending interrupt and sleep mode is exited immediately.
Note 3 Upon wakeup, the instruction immediately after the
sleep instruction is executed before the interrupt service rou-
tine (if enabled). The instruction after the sleep instruction is
prefetched before the system actually goes to sleep. Thus,
when an interrupt occurs to wake the system up, the
prefetched instruction executes and the interrupt service
routine is executed. (If the Global Interrupt Enable is not set,
instruction execution continues where it left off before
sleep.)
Note 4 If the Global Interrupt Enable bit is disabled, it is
safely enabled just before the instruction that writes the
SLEEP bit. It is usually undesirable to get an interrupt on the
instruction boundary just before writing the SLEEP bit. This
means that upon return from the interrupt, the sleep com-
mand is executed, possibly bypassing any firmware prepa-
rations that are necessary to go to sleep. To prevent this,
disable interrupts before making preparations. After sleep
preparations, enable global interrupts and write the SLEEP
bit with the two consecutive instructions as follows.
and f,~01h // disable global interrupts
// (prepare for sleep, could
// be many instructions)
or f,01h // enable global interrupts
mov reg[ffh],08h // Set the sleep bit
Because of the timing of the Global Interrupt Enable instruc-
tion, it is not possible for an interrupt to occur immediately
after that instruction. The earliest for the interrupt to occur is
after the next instruction (write to the SLEEP bit) is exe-
cuted. If an interrupt is pending, the sleep instruction is exe-
cuted; but as described in Note 1, the sleep instruction is
ignored. The first instruction executed after the ISR is the
instruction after sleep.
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