Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 21
10. External Crystal Oscillator (ECO)
This chapter briefly explains the External Crystal Oscillator (ECO) and its associated registers. The 32.768 kHz external crys-
tal oscillator circuit allows the user to replace the internal low speed oscillator with a more precise time source at low cost and
low power. For a complete table of the External Crystal Oscillator registers, refer to the
“Summary Table of the Core Regis-
ters” on page 32 . For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on
page 47 .
10.1 Architectural Description
The External Crystal Oscillator (ECO) circuit uses an inex-
pensive watch crystal and two small value capacitors as
external components, with all other components being on
the PSoC device. The crystal oscillator may be configured to
provide a reference to the Internal Main Oscillator (IMO) in
PLL mode, for generating a 24 MHz system clock.
The XTALIn and XTALOut pins support connection of a
32.768 kHz watch crystal. To use the external crystal, bit 7 of
the Oscillator Control 0 register (OSC_CR0) must be set
(the default is off). The only external components needed
are the crystal and the two capacitors that connect to Vdd.
Note that transitions between the internal and external oscil-
lator domains may produce glitches on the clock bus.
During the process of activating the ECO, there must be a
hold-off period before using it as the 32.768 kHz source.
This hold-off period is partially implemented in hardware
using the sleep timer. Firmware must set up a sleep period
of one second (maximum ECO
settling time ), and then
enable the ECO in the OSC_CR0 register. At the one sec-
ond time-out (the sleep interrupt), the switch is made by
hardware to the ECO. If the ECO is subsequently deacti-
vated, the Internal Low Speed Oscillator (ILO) is again acti-
vated and the switch is made back to the ILO immediately.
The ECO Exists bit (ECO EX, bit 2 in the CPU_SCR1 regis-
ter) is used to control whether the switch-over is allowed or
locked. This is a write once bit. It is written early in code exe-
cution after a Power On Reset (POR) or External Reset
(XRES) event. A ‘1’ in this bit indicates to the hardware that
a crystal exists in the system, and firmware is allowed to
switch back and forth between ECO and ILO operation. If
the bit is ‘0’, switch-over to the ECO is locked out. The ECO
Exists Written bit (ECO EXW, bit 3 in the CPU_SCR1 regis-
ter) is read only and is set on the first write to this register.
When this bit is ‘1’, it indicates that the state of ECO EX is
locked. This is illustrated in
Figure 10-1 .
Note Bits 3 and 2 (ECO EXW and ECO EX, respectively) in
the CPU_SCR1 register cannot be used by the CY8C27x43
for silicon revision A, and by the CY8C24533, CY8C23533,
CY8C23433, CY8C23533, CY8C23433, CY8C24633,
CY8C24x23, and CY8C22x13 PSoC devices.
Figure 10-1. Transition Between ECO and ILO Operation
The firmware steps involved in switching between the Inter-
nal Low Speed Oscillator (ILO) to the 32.768 kHz External
Crystal Oscillator (ECO) are as follows.
1. At reset, the PSoC device begins operation, using the
ILO.
2. Set the ECO EX bit to allow crystal operation.
3. Select a sleep interval of one second, using bits[4:3] in
the Oscillator Control 0 register (OSC_CR0), as the
oscillator stabilization interval.
4. Enable the ECO by setting bit [7] in Oscillator Control 0
register (OSC_CR0) to ‘1’.
(Default
POR State)
ECO Inactive
ILO Active
ECO Active
ILO Inactive
(User has
stated that
ECO is in use.)
Transitions allowed only if write once
"ECO Exists" register bit is set.
Clear OSC_CR0[7] to
immediately revert back
to ILO as 32 kHz
source.
Set OSC_CR0[7] to
activate the ECO, then
on the next Sleep
interrupt, ECO becomes
the 32.768 kHz source.