Cypress PSoC CY8C23533, Technical Reference Manual

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38 Document # 001-20559 Rev. *D
CPU Core (M8C)
2.5 Instruction Formats
The M8C has a total of seven instruction formats which use
instruction lengths of one, two, and three bytes. All instruc-
tion bytes are fetched from the program memory (Flash),
using an address and data bus that are independent from
the address and data buses used for register and RAM
access.
While examples of instructions are given in this section,
refer to the
PSoC Designer Assembly Language User Guide
for detailed information on individual instructions.
2.5.1 One-Byte Instructions
Many instructions, such as some of the
MOV
instructions,
have single-byte forms because they do not use an address
or data as an operand. As shown in
Table 2-3 , one-byte
instructions use an 8-bit opcode. The set of one-byte
instructions can be divided into four categories, according to
where their results are stored.
The first category of one-byte instructions are those that do
not update any registers or RAM. Only the one-byte
NOP
and
SSC
instructions fit this category. While the program
counter is incremented as these instructions execute, they
do not cause any other internal M8C registers to be
updated, nor do these instructions directly affect the register
space or the RAM address space. The
SSC
instruction
causes SROM code to run, which modifies RAM and the
M8C internal registers.
The second category has only the two
PUSH
instructions in
it. The
PUSH
instructions are unique, because they are the
only one-byte instructions that cause a RAM address to be
modified. These instructions automatically increment the SP.
The third category has only the
HALT
instruction in it. The
HALT
instruction is unique, because it is the only one-byte
instruction that causes a user register to be modified. The
HALT
instruction modifies user register space address FFh
(CPU_SCR register).
The final category for one-byte instructions are those that
cause updates of the internal M8C registers. This category
holds the largest number of instructions:
ASL
,
ASR
,
CPL
,
DEC
,
INC
,
MOV
,
POP
,
RET
,
RETI
,
RLC
,
ROMX
,
RRC
,
SWAP
. These instructions can cause the A, X, and SP regis-
ters or SRAM to update.
2.5.2 Two-Byte Instructions
The majority of M8C instructions are two bytes in length.
While these instructions can be divided into categories iden-
tical to the one-byte instructions, this would not provide a
useful distinction between the three two-byte instruction for-
mats that the M8C uses.
The first two-byte instruction format, shown in the first row of
Table 2-4 , is used by short jumps and calls:
CALL
,
JMP
,
JACC
,
INDEX
,
JC
,
JNC
,
JNZ
,
JZ
. This instruction format
uses only four bits for the instruction opcode, leaving 12 bits
to store the relative destination address in a two’s-comple-
ment form. These instructions can change program execu-
tion to an address relative to the current address by -2048 or
+2047.
The second two-byte instruction format, shown in the sec-
ond row of
Table 2-4 , is used by instructions that employ the
Source Immediate addressing mode (see “Source Immedi-
ate” on page 39 ). The destination for these instructions is an
internal M8C register, while the source is a constant value.
An example of this type of instruction would be
ADD A, 7
.
The third two-byte instruction format, shown in the third row
of
Table 2-4 , is used by a wide range of instructions and
addressing modes. The following is a list of the addressing
modes that use this third two-byte instruction format:
■ Source Direct ( ADD A, [7] )
■ Source Indexed ( ADD A, [X+7] )
■ Destination Direct ( ADD [7], A )
■ Destination Indexed ( ADD [X+7], A )
■ Source Indirect Post Increment ( MVI A, [7] )
■ Destination Indirect Post Increment ( MVI [7], A )
For more information on addressing modes see “Addressing
Modes” on page 39 .
Table 2-3. One-Byte Instruction Format
Byte 0
8-Bit Opcode
Table 2-4. Two-Byte Instruction Formats
Byte 0 Byte 1
4-Bit Opcode 12-Bit Relative Address
8-Bit Opcode 8-Bit Data
8-Bit Opcode 8-Bit Address