Cypress PSoC CY8C23533, Technical Reference Manual

Page: 363 / 410

Document # 001-20559 Rev. *D 299
I2C
Bit 4: Stop IE (Interrupt Enable). When this bit is set, a
master or slave can interrupt on stop detection. The status
bit associated with this interrupt is the Stop Status bit in the
Slave Status and Control register. When the Stop Status bit
transitions from ‘0’ to ‘1’, the interrupt is generated. It is
important to note that the Stop Status bit is not automatically
cleared. Therefore, if it is already set, no new interrupts are
generated until it is cleared by firmware.
Bits 3 and 2: Clock Rate[1:0]. These bits offer a selection
of three sampling and bit rates. All block clocking is based
on the SYSCLK input, which is nominally 24 MHz (unless
the PSoC device is in external clocking mode). The sam-
pling rate and the baud rate are determined as follows:
■ Sample Rate = SYSCLK/Pre-scale Factor
■ Baud Rate = 1/(Sample Rate x Samples per Bit)
The nominal values, when using the internal 24 MHz oscilla-
tor, are shown in
Table 28-2 .
When clocking the input with a frequency other than 24 MHz
(for example, clocking the PSoC device with an external
clock), the baud rates and sampling rates scale accordingly.
Whether the block works in a Standard Mode or Fast Mode
system depends on the sample rate. The sample rate must
be sufficient to resolve bus events, such as start and stop
conditions. (See the Phillips Semiconductors’ I
2
C™ Specifi-
cation, version 2.1, for minimum start and stop hold times.)
Bit 1: Enable Master. When this bit is set, the Master Sta-
tus and Control register is enabled (otherwise it is held in
reset) and I2C transfers can be initiated in Master mode.
When the master is enabled and operating, the block clocks
the I2C bus at one of three baud rates, defined in the Clock
Rate register. When operating in Master mode, the hard-
ware is multi-master capable, implementing both clock syn-
chronization and arbitration. If the Slave Enable bit is not
set, the block operates in Master Only mode. All external
start conditions are ignored (although the Bus Busy status
bit still keeps track of bus activity). Block enable synchro-
nizes to the SYSCLK clock input (
see “Timing Diagrams” on
page 304 ).
Bit 0: Enable Slave. When the slave is enabled, the block
generates an interrupt on any start condition and an address
byte that it receives, indicating the beginning of an I2C
transfer. When operating as a slave, the block is clocked
from an external master. Therefore, the block works at any
frequency up to the maximum defined by the currently
selected clock rate. The internal clock is only used in Slave
mode to ensure that there is adequate set up time from data
output to the next clock on the release of a slave stall. When
the Enable Slave and Enable Master bits are both ‘0’, the
block is held in reset and all status cleared. See
Figure 28-3
for a description of the interaction between the Master/Slave
Enable bits. Block enable synchronizes to the SYSCLK
clock input (
see “Timing Diagrams” on page 304 ).
For additional information, refer to the I2C_CFG register on
page 94 .
Table 28-2. I
2
C Clock Rates
Clock Rate
[1
:0]
I2
C M
o
de
SYSCLK
P
re
-scal
e
Fac
tor
Sam
p
le
s
per Bit
In
te
rn
al
Sa
m
p
lin
g
Freq.
/Pe
ri
od
(24 MHz)
Mas
ter
Baud Rate
(n
o
m
in
a
l)
St
a
rt
/St
o
p
Hold T
ime
(8 cl
ocks)
00b Standard /16 16 1.5 MHz/667 ns 93.75 kHz 5.3

s
01b Fast /4 16 6 MHz/167 ns 375 kHz 1.33

s
10b Standard /16 32 1.5 MHz/667 ns 46.8 kHz 10.7

s
11b Reserved
Table 28-3. Enable Master/Slave Block Operation
Enable
Master Enable
Slave
Block Operation
No No Disabled:
The block is disconnected from the GPIO pins, P1[5]
and P1[7]. (The pins may be used as general purpose
IO.) When either the master or slave is enabled, the
GPIO pins are under control of the I2C hardware and
are unavailable.
All internal registers (except I2C_CFG) are held in
reset.
No Yes Slave Only Mode:
Any external start condition causes the block to start
receiving an address byte. Regardless of the current
state, any start resets the interface and initiates a
receive operation. Any stop causes the block to revert
to an idle state
The I2C_MSCR register is held in reset.
Yes No Master Only Mode:
External Start conditions are ignored in this mode. No
Byte Complete interrupts on external traffic are gener-
ated, but the Bus Busy status bit continues to capture
Start and Stop status, and thus may be polled by the
master to determine if the bus is available.
Full multi-master capability is enabled, including clock
synchronization and arbitration.
The block generates a clock based on the setting in
the Clock Rate register
Yes Yes Master/Slave Mode:
Both master and slave are operational in this mode.
The block may be addressed as a slave, but firmware
may also initiate Master mode transfers.
In this configuration, when a master loses arbitration
during an address byte, the hardware reverts to Slave
mode and the received byte generates a slave
address interrupt.