Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 169
15. Array Digital Interconnect (ADI)
This chapter presents the Array Digital Interconnect (ADI). The digital PSoC array uses a scalable architecture that is
designed to support from one to four digital PSoC rows, as defined in the
Row Digital Interconnect (RDI) chapter on page
171 . The digital PSoC array does not have any configurable interconnect; therefore, there are no associated registers in this
chapter.
15.1 Architectural Description
The Array Digital Interconnect (ADI) for the CY8C24533, CY8C23533, CY8C23433CY8C24633 PSoC devices is shown in
Figure 15-1 . The ADI is not configurable; therefore, the information in this chapter is provided to improve the reader’s under-
standing of the structure.
Figure 15-1. Digital PSoC Block Array Structure
Figure 15-1 illustrates how all rows are connected to the
same globals, clocks, and so on. The figure also illustrates
how the broadcast clock nets (BCrowx) are connected.
The digital PSoC blocks in the digital array are arranged into
rows and the ADI provides a regular interconnect architec-
ture between the Global Digital Interconnect (GDI) and the
Row Digital Interconnect (RDI). The most important aspect
of the ADI and the digital PSoC rows is that all digital PSoC
rows have the same connections to global inputs and out-
puts. The connections that make a row’s position unique are
explained as follows.
■ Register Address : Rows and the blocks within them
need to have unique register addresses.
■ Interrupt Priority : Each digital PSoC block has its own
interrupt priority and vector. A row’s position in the array
determines the relative priority of the digital PSoC blocks
within the row. The lower the row number, the higher the
interrupt priority, and the lower the interrupt vector
address.
■ Broadcast : Each digital PSoC row has an internal
broadcast net that may be either driven internally, by
one of the four digital PSoC blocks, or driven externally.
In the case where the broadcast net is driven externally,
the source may be any one of the other rows in the
array. Therefore, depending on the row’s position in the
array, it has different options for driving its broadcast net.
■ Chaining Position : Rows in the array form a string of
digital blocks equal in length to the number of rows multi-
plied by four. The first block in the first row and the last
block in the last row are not connected; therefore, the
array does not form a loop. The first row in the array has
its previous
chaining inputs tied low. If there is a second
row in the array, the next chaining outputs are connected
to the next row. For the last row in the array, the next
inputs are tied low.
GOE[7:0]
GOO[7:0]
Digital PSoC Block Row 0
GIO[7:0]
GlE[7:0]
BCx
BCy
BCz
BCw
Previous Block Clock
Previous Block Data
FPB
TPB
DB[7:0]
DBI
TNB
FNB
INT[3:0]
VC3 SY
SC
LK
X
2
VC1 VC2 CL
K
3
2
K
ACM
P
[3
:0
]
DBB00 DBB01 DCB02 DCB03