Application Note
7 of 42
001-65209 Rev.*I
2021-03-19
Getting Started with FX2LP™
FX2LP Introduction
The Slave FIFO interface:
•
Provides a data bus that is 8 or 16 bits wide.
•
Operates either asynchronously (no clock) or synchronously (with clock).
•
Accepts an external clock or uses an internal FX2LP 30-/48-MHz clock (in synchronous mode), which it makes
available on the CLKOUT pin. There is no need of crystal for the external peripheral device if it can work
based on the clock provided on the CLKOUT pin.
•
Has output flags indicating FIFO status, such as full and empty.
•
Has control inputs OE#, RD#, and WR#.
•
Has two address lines to select one of four FX2LP FIFOs.
•
Automatically launches USB transfers when the FIFO fills or empties.
•
Has a control signal (PKETND)
that the interface device can use to launch a “short packet” (FIFO has data
but is not full). Short packets routinely occur as the final packet of a long USB transfer.
In systems where data processing is not required in FX2LP, the FX2LP Slave FIFO interface requires minimal
firmware just to select the Slave FIFO interface and to configure the flags to indicate the status of the FIFOs.
Waveforms and timing values for the Slave FIFO interface are given in the
3.1.2.2
General Programmable Interface
Not all external controllers are designed to connect to a FIFO. Therefore, FX2LP provides a high-speed interface,
GPIF (shown in
), which provides direct connection to common interfaces, such as disk drives, FPGAs,
and ASICs, without requiring additional glue logic. The GPIF’s core is a state machine—
you must develop
waveforms using
to control the state machine. The GPIF is driven by one of the four Waveform
Descriptors, which are data structures containing all the waveform information. GPIF Designer relieves the
designer of understanding the descriptor formats. It uses the graphical waveform entry to create a C-language
source file, which can be included in an FX2LP project.
Pipe
(FIFO)
G
P
IF
Data
Clock
ADDR
Control
RDY
STATE
Waveform
Descriptors
Figure 4
FX2LP GPIF Interface
The GPIF (see the
•
Provides a data bus that is 8 or 16 bits wide.
•
Operates synchronously (with clock).
•
Accepts an external clock or uses an internal FX2LP 30-/48-MHz clock (in synchronous mode), which it makes
available on a device pin.
•
Provides nine address outputs. Addresses can be initialized and incremented on a clock-by-clock basis.
•
Provides six control (CTL) and ready (RDY) signals. Six control outputs are also programmable on a clock-by-
clock basis. As a simple example, RD# and WR# strobes can be created with programmable durations and
polarities using these control signals. Six ready inputs can be tested in a GPIF state machine to read status
and perform interface synchronization. Three state outputs (GSTATE [2:0]) indicate the GPIF state, useful for
debugging with a logic analyzer.
