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Cypress EZ-OTG CY7C67200, Specification Sheet

The Cypress EZ-OTG CY7C67200 is a high-performance USB peripheral controller. It offers versatile connectivity options and advanced features. To get a complete understanding of its capabilities, make sure to download the free "Specification Sheet" and user "manual" from our website, manualshive.com.

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CY7C67200

Document #: 38-08014 Rev. *G

Page 37 of 78

Reset Interrupt Flag

 (Bit 8)

The Reset Interrupt Flag bit indicates if the USB Reset
Detected interrupt has triggered.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP7 Interrupt Flag

 (Bit 7)

The EP7 Interrupt Flag bit indicates if the endpoint seven
(EP7) Transaction Done interrupt has triggered. An EPx
Transaction Done interrupt triggers when any of the following
responses or events occur in a transaction for the device’s
given EP: send/receive ACK, send STALL, Timeout occurs, IN
Exception Error, or OUT Exception Error. In addition, if the
NAK Interrupt Enable bit in the Device n Endpoint Control
register is set, this interrupt also triggers when the device
NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP6 Interrupt Flag

 (Bit 6)

The EP6 Interrupt Flag bit indicates if the endpoint six (EP6)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP5 Interrupt Flag

 (Bit 5)

The EP5 Interrupt Flag bit indicates if the endpoint five (EP5)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP4 Interrupt Flag

 (Bit 4)

The EP4 Interrupt Flag bit indicates if the endpoint four (EP4)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP3 Interrupt Flag

 (Bit 3)

The EP3 Interrupt Flag bit indicates if the endpoint three (EP3)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP2 Interrupt Flag

 (Bit 2)

The EP2 Interrupt Flag bit indicates if the endpoint two (EP2)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP1 Interrupt Flag

 (Bit 1)

The EP1 Interrupt Flag bit indicates if the endpoint one (EP1)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

EP0 Interrupt Flag

 (Bit 0)

The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.

1: 

Interrupt triggered

0:

 Interrupt did not trigger

Reserved

All reserved bits must be written as ‘0’.

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Summary of Contents for EZ-OTG CY7C67200

Page 1: ...port interface HPI with DMA Mailbox data path for an external processor to directly access all on chip memory and control on chip SIEs Fast serial port supports from 9600 baud to 2 0M baud SPI supports both master and slave Supports 12 MHz external crystal or clock 2 7V to 3 6V power supply voltage Package option 48 pin FBGA Typical Applications EZ OTG is a very powerful and flexible dual role USB...

Page 2: ...e used for program code or data Interrupts EZ OTG provides 128 interrupt vectors The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts General Timers and Watchdog Timer EZ OTG has two built in programmable timers and a watchdog timer All three timers can generate an interrupt to the EZ OTG Power Management EZ OTG has one main power saving mode Sleep Slee...

Page 3: ...G Features Internal Charge Pump to supply and control VBUS VBUS Valid Status above 4 4V VBUS Status for 2 4V VBUS 0 8V ID Pin Status Switchable 2 Kohm internal discharge resistor on VBUS Switchable 500 ohm internal pull up resistor on VBUS Individually switchable internal pull up and pull down resistors on the USB data lines OTG Pins General Purpose IO Interface EZ OTG has up to 25 GPIO signals av...

Page 4: ... timing for the active inactive master SPI clock Auto or manual control for master mode slave select signal Complete access to internal memory SPI Pins The SPI port has a few different pin location options as shown in Table 7 The pin location is selectable via the GPIO Control register 0xC006 High Speed Serial Interface EZ OTG provides an HSS interface The HSS interface is a programmable serial co...

Page 5: ...al memory Complete control of SIEs through HPI Dedicated HPI Status register HPI Pins The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 10 below Charge Pump Interface VBUS for the USB On The Go OTG port can be produced by EZ OTG using its built in charge pump and some external components The circuit connections should look similar to Figure 1 be...

Page 6: ...th a capacitance of at least 2 2 µF Figure 3 shows how to connect the power supply when the booster circuit is not being used Booster Pins Crystal Interface The recommended crystal circuit to be used with EZ OTG is shown in Figure 4 If an oscillator is used instead of a crystal circuit connect it to XTALIN and leave XTALOUT uncon nected For further information on the crystal requirements see Table...

Page 7: ...n processor rather then EZ OTG s own 16 bit internal CPU An external host processor may interface to EZ OTG through one of the following three interfaces in coprocessor mode HPI mode a 16 bit parallel interface with up to 16 MBytes transfer rate HSS mode a serial interface with up to 2M baud transfer rate SPI mode a serial interface with up to 2 Mbits s transfer rate At bootup GPIO 31 30 determine...

Page 8: ...y setting the Sleep Enable bit 1 of the Power Control register 0xC00A During Sleep mode USB Suspend the following events and states are true GPIO pins maintain their configuration during sleep in suspend External Memory Address pins are driven low XTALOUT is turned off Internal PLL is turned off Firmware must disable the charge pump OTG Control register 0xC098 causing OTGVBUS to drop below 0 2V Ot...

Page 9: ...er 24 KB of addressable memory mapped from 0x0000 to 0xFFFF This 24 KB contains both program and data space and is byte addressable Figure 6 shows the various memory region address locations Internal Memory Of the internal memory 15 KB is allocated for user s program and data code The lower memory space from 0x0000 to 0x04A2 is reserved for interrupt vectors general purpose registers USB control r...

Page 10: ...MS result bit is not 1 Overflow Flag Bit 2 The Overflow Flag bit indicates if an overflow condition has occurred An overflow condition can occur if an arithmetic result was either larger than the destination operand size for addition or smaller than the destination operand should allow for subtraction 1 Overflow occurred 0 Overflow did not occur Carry Flag Bit 1 The Carry Flag bit indicates if an ...

Page 11: ... bits must be written as 0 Hardware Revision Register 0xC004 R Figure 9 Revision Register Register Description The Hardware Revision register is a read only register that indicates the silicon revision number The first silicon revision is represented by 0x0101 This number is increased by one for each new silicon revision Revision Bits 15 0 The Revision field contains the silicon revision number Bi...

Page 12: ...hat selects the operating speed of the processor as defined in Table 18 Reserved All reserved bits must be written as 0 Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Reserved CPU Speed Read Write R W R W R W R W Default 0 0 0 0 1 1 1 1 Table 18 CPU Speed Definition CPU Speed 3 0 Processor Speed 0000 48 MHz 1 0001 48 MHz 2 0010 48 MHz 3 0011 4...

Page 13: ...s or disables a wakeup condition to occur on a falling SPI_nSS input transition The processor may take several hundreds of microseconds before being operational after wakeup Therefore the incoming data byte that causes the wakeup will be discarded 1 Enable wakeup on falling SPI nSS input transition 0 Disable SPI_nSS interrupt HPI Wake Enable Bit 7 The HPI Wake Enable bit enables or disables a wake...

Page 14: ...terrupts Host 2 USB Done Host 2 USB SOF EOP Host 2 WakeUp Insert Remove Device 2 Reset Device 2 SOF EOP or WakeUp from USB Device 2 Endpoint n 1 Enable Host 2 and Device 2 interrupt 0 Disable Host 2 and Device 2 interrupt Host Device 1 Interrupt Enable Bit 8 The Host Device 1 Interrupt Enable bit enables or disables all of the following Host Device 1 hardware interrupts Host 1 USB Done Host 1 USB ...

Page 15: ... interrupt 0 Disable TM1 interrupt Timer 0 Interrupt Enable Bit 0 The Timer 0 Interrupt Enable bit enables or disables the TImer0 Interrupt Enable When this bit is reset all pending Timer 0 interrupts are cleared 1 Enable TM0 interrupt 0 Disable TM0 interrupt Reserved All reserved bits must be written as 0 Breakpoint Register 0xC014 R W Figure 13 Breakpoint Register Register Description The Breakp...

Page 16: ... LS Pull up Enable bit enables or disables a low speed pull up resistor pull up on D for testing 1 Enable low speed pull up resistor on D 0 Pull up resistor is not connected on D FS Pull up Enable Bit 4 The FS Pull up Enable bit enables or disables a full speed pull up resistor pull up on D for testing 1 Enable full speed pull up resistor on D 0 Pull up resistor is not connected on D Force Select ...

Page 17: ... register until a reset In doing so the Watchdog timer can be set up and enabled permanently so that it can only be cleared on reset the WDT Enable bit is ignored 1 Watchdog timer permanently set 0 Watchdog timer not permanently set WDT Enable Bit 1 The WDT Enable bit enables or disables the Watchdog timer 1 Enable Watchdog timer operation 0 Disable Watchdog timer operation Reset Strobe Bit 0 The ...

Page 18: ...are covered in Section USB Device Only Registers on page 28 USB n Control Register R W USB 1 Control Register 0xC08A USB 2 Control Register 0xC0AA Figure 17 USB n Control Register Register Description The USB n Control register is used in both host and device mode It monitors and controls the SIE and the data lines of the USB ports This register can be accessed by the HPI interface Bit 15 14 13 12...

Page 19: ... powered down and can not transmit or received USB packets but can still monitor for a wakeup condition 1 Enable suspend 0 Disable suspend Port A SOF EOP Enable Bit 0 The Port A SOF EOP Enable bit is only applicable in host mode In Device mode this bit must be written as 0 In host mode this bit enables or disables SOFs or EOPs for Port A Either SOFs or EOPs will be generated depending on the LOA b...

Page 20: ...le Bit 5 The Sync Enable bit synchronizes the transfer with the SOF packet in full speed mode and the EOP packet in low speed mode 1 The next enabled packet will be transferred after the SOF or EOP packet is transmitted 0 The next enabled packet will be transferred as soon as the SIE is free ISO Enable Bit 4 The ISO Enable bit enables or disables an Isochronous trans action 1 Enable Isochronous tr...

Page 21: ... value is used to determine how many bytes to transmit or the maximum number of bytes to receive If the number of received bytes is greater then the Host Count value then an overflow condition will be flagged by the Overflow bit in the Host n Endpoint Status register Count Bits 9 0 The Count field sets the value for the current transaction data packet length This value is retained when switching b...

Page 22: ... the last transaction does not equal the maximum Host Count specified in the Host n Count register A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags bits 11 and 10 respec tively should be checked to determine which event occurred 1 An overflow or underflow condition occurred 0 An overflow or underflow condition did not occur Sequence Status Bit 3 The ...

Page 23: ...ription The Host n PID register is a write only register that provides the PID and Endpoint information to the USB SIE to be used in the next transaction PID Select Bits 7 4 The PID Select field defined as in Table 26 ACK and NAK tokens are automatically sent based on settings in the Host n Control register and do not need to be written in this register Endpoint Select Bits 3 0 The Endpoint field ...

Page 24: ...w condition occurs Result 15 10 is set to 111111 a 2 s complement value indicating the additional byte count of the received packet If an underflow condition occurs Result 15 0 indicates the excess byte count number of bytes not used Reserved All reserved bits must be written as 0 Host n Device Address Register W Host 1 Device Address Register 0xC088 Host 2 Device Address Register 0xC0A8 Figure 24...

Page 25: ...F EOP timer interrupt 0 Disable SOF EOP timer interrupt Port A Wake Interrupt Enable Bit 6 The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A 1 Enable remote wakeup interrupt for Port A 0 Disable remote wakeup interrupt for Port A Port A Connect Change Interrupt Enable Bit 4 The Port A Connect Change Interrupt Enable bit enables or disables the Connect ...

Page 26: ... indicates remote wakeup on Port A 1 Interrupt triggered 0 Interrupt did not trigger Port A Connect Change Interrupt Flag Bit 4 The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A This bit triggers 1 on either a rising edge or falling edge of a USB Reset condition device inserted or removed Together with the Port A SE0 Status bit it can be de...

Page 27: ...P counter duration Reserved All reserved bits must be written as 0 Host n SOF EOP Counter Register R Host 1 SOF EOP Counter Register 0xC094 Host 2 SOF EOP Counter Register 0xC0B4 Figure 28 Host n SOF EOP Counter Register Register Description The Host n SOF EOP Counter register contains the current value of the SOF EOP down counter This value can be used to determine the time remaining in the curre...

Page 28: ...trol Register Device 1 0x0200 Device 2 0x0280 Device n Endpoint 1 Control Register Device 1 0x0210 Device 2 0x0290 Device n Endpoint 2 Control Register Device 1 0x0220 Device 2 0x02A0 Device n Endpoint 3 Control Register Device 1 0x0230 Device 2 0x02B0 Device n Endpoint 4 Control Register Device 1 0x0240 Device 2 0x02C0 Device n Endpoint 5 Control Register Device 1 0x0250 Device 2 0x02D0 Device n ...

Page 29: ... Interrupt Enable register must also be set When a NAK is sent to the host the corresponding EP Interrupt Flag in the Device n Status register will be set In addition the NAK Flag in the Device n Endpoint n Status register will be set 1 Enable NAK interrupt 0 Disable NAK interrupt Direction Select Bit 2 The Direction Select bit needs to be set according to the expected direction of the next data s...

Page 30: ...dpoint n Address register Address Bits 15 0 The Address field sets the base address for the current transaction on a signal endpoint Device n Endpoint n Count Register R W Device n Endpoint 0 Count Register Device 1 0x0204 Device 2 0x0284 Device n Endpoint 1 Count Register Device 1 0x0214 Device 2 0x0294 Device n Endpoint 2 Count Register Device 1 0x0224 Device 2 0x02A4 Device n Endpoint 3 Count R...

Page 31: ...re and does not need to be cleared by firmware There are a total of eight endpoints for each of the two ports All endpoints have the same definition for their Device n Endpoint n Status register The Device n Endpoint n Status register is a memory based register that must be initialized to 0x0000 before USB Device operations are initiated After initialization this register must not be written to ag...

Page 32: ...s are stored at memory location 0x0300 for Device 1 and 0x0308 for Device 2 Setup packets are always accepted regardless of the Direction Select and Arm Enable bit settings as long as the Device n EP n Control register Enable bit is set 1 Setup packet was received 0 Setup packet was not received Sequence Flag Bit 3 The Sequence Flag bit indicates whether the last data toggle received was a DATA1 o...

Page 33: ...gth differs from the value specified in the Device n Endpoint n Count register the Length Exception Flag bit in the Device n Endpoint n Status register will be set The value in this register is only considered when the Length Exception Flag bit is set and the Error Flag bit is not set both bits are in the Device n Endpoint n Status register The Device n Endpoint n Count Result register is a memory...

Page 34: ...upt 0 Disable SOF EOP Received interrupt Reset Interrupt Enable Bit 8 The Reset Interrupt Enable bit enables or disables the USB Reset Detected interrupt 1 Enable USB Reset Detected interrupt 0 Disable USB Reset Detected interrupt EP7 Interrupt Enable Bit 7 The EP7 Interrupt Enable bit enables or disables an endpoint seven EP7 Transaction Done interrupt An EPx Transaction Done interrupt triggers w...

Page 35: ...s this interrupt 1 Enable EP3 Transaction Done interrupt 0 Disable EP3 Transaction Done interrupt EP2 Interrupt Enable Bit 2 The EP2 Interrupt Enable bit enables or disables an endpoint two EP2 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s given Endpoint send receive ACK send STALL Timeout...

Page 36: ...r Port 1A When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4 4V This bit is only available for Device 1 and is a reserved bit in Device 2 1 Interrupt triggered 0 Interrupt did not trigger ID Interrupt Flag Bit 14 The ID Interrupt Flag bit indicates the status of the OTG ID interrupt only for Port 1A When enabled this interrupt triggers on both the rising and fall...

Page 37: ...rrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger EP3 Interrupt Flag Bit 3 The EP3 Interrupt Flag bit indicates if the endpoint three EP3 Transaction Done interrupt has triggered An EPx Transaction Done interrupt triggers when any of the following responses or events oc...

Page 38: ...ister 0xC094 Device 2 SOF EOP Count Register 0xC0B4 Figure 39 Device n SOF EOP Count Register Register Description The Device n SOF EOP Count register must be written with the time expected between receiving a SOF EOPs If the SOF EOP counter expires before an SOF EOP is received an SOF EOP Timeout Interrupt can be generated The SOF EOP Timeout Interrupt Enable and SOF EOP Timeout Interrupt Flag ar...

Page 39: ...abled D Pull up Enable Bit 8 The D Pull up Enable bit enables or disables a pull up resistor on the OTG D data line 1 OTG D dataline pull up resistor enabled 0 OTG D dataline pull up resistor disabled D Pull down Enable Bit 7 The D Pull down Enable bit enables or disables a pull down resistor on the OTG D data line 1 OTG D dataline pull down resistor enabled 0 OTG D dataline pull down resistor dis...

Page 40: ...t 11 The SAS Enable bit when in SPI mode reroutes the SPI port SPI_nSSI pin to GPIO 15 rather then GPIO 9 1 Reroute SPI_nss to GPIO 15 0 Leave SPI_nss on GPIO 9 Mode Select Bits 10 8 The Mode Select field selects how GPIO 15 0 and GPIO 24 19 are used as defined in Table 30 Table 29 GPIO Registers Register Name Address R W GPIO Control Register 0xC006 R W GPIO0 Output Data Register 0xC01E R W GPIO0...

Page 41: ...o GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19 When read this register reads back the last data written not the data on pins configured as inputs see Input Data Register Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin Reserved All reserved bits must be written as 0 GPIO 1 Output Data Register 0xC024 R W Figure 43 GPIO n Output Data Register ...

Page 42: ... Data register reads from GPIO31 to GPIO19 Every bit represents the voltage of that GPIO pin GPIO 0 Direction Register 0xC022 R W Figure 46 GPIO 0 Direction Register Bit 15 14 13 12 11 10 9 8 Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 Read Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Read Write R R R R R R ...

Page 43: ...19 When any bit of this register is set to 1 the corresponding GPIO data pin becomes an output When any bit of this register is set to 0 the corresponding GPIO data pin becomes an input Reserved All reserved bits must be written as 0 HSS Registers There are eight registers dedicated to HSS operation Each of these registers are covered in this section and summarized in Table 31 Bit 15 14 13 12 11 1...

Page 44: ...eady and Receive Packet Ready interrupts Done Interrupt Enable Bit 8 The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts 1 Enable the Transmit Done and Receive Done interrupts 0 Disable the Transmit Done and Receive Done interrupts Transmit Done Interrupt Flag Bit 7 The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt ...

Page 45: ...only bit that indicates if the HSS receive FIFO is full with eight bytes 1 HSS receive FIFO is full 0 HSS receive FIFO is not full Receive Ready Flag Bit 0 The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty 1 HSS receive FIFO is not empty one or more bytes is reading for reading 0 HSS receive FIFO is empty HSS Baud Rate Register 0xC072 R W Figure 49 HSS Baud ...

Page 46: ...ster Register Description The HSS Data register contains data received on the HSS port not for block receive mode when read This receive data is valid when the Receive Ready bit of the HSS Control register is set to 1 Writing to this register initiates a single byte transfer of data The Transmit Ready Flag in the HSS Control register must read 1 before writing to this register this avoids disrupti...

Page 47: ...start the block receive transfer As each byte is received this register value is decre mented When read this register indicates the remaining length of the transfer Counter Bits 9 0 The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF 1023 or 2048 bytes When the transfer is complete this register returns 0x03FF until reloaded Reserved All reserved bits must...

Page 48: ...e is equal to the word count minus one giving a maximum value of 0x03FF 1023 or 2048 bytes When the transfer is complete this register returns 0x03FF until reloaded Reserved All reserved bits must be written as 0 HPI Registers There are five registers dedicated to HPI operation In addition there is an HPI status port which can be address over HPI Each of these registers is covered in this section ...

Page 49: ...ort to become the HPI_INTR signal and also readable in the HPI Status register The bits in this register select where the interrupts are routed The individual interrupt enable is handled in the SIE interrupt enable register VBUS to HPI Enable Bit 15 The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal t...

Page 50: ... to 11 the most significant data byte goes to HPI_D 7 0 and the least significant byte goes to HPI_D 15 8 Resume2 to HPI Enable Bit 7 The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port Resume1 to HPI Enable Bit 6 The Resume1 to HPI Enable bit routes the USB Resum...

Page 51: ...ster When the CY7C67200 reads this register the HPI Mailbox RX Full interrupt automatically gets cleared If enabled the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register The HPI Mailbox TX Empty interrupt is automatically cleared when the CY7C67200 writes to this register In addition when the CY7C67200 writes to this register the HPI_INTR signal on t...

Page 52: ...errupt triggered 0 Interrupt did not trigger Mailbox In Flag Bit 8 The Mailbox In Flag bit is a read only bit that indicates if a message is ready in the incoming mailbox This interrupt clears when on chip CPU reads from the HPI Mailbox register 1 Interrupt triggered 0 Interrupt did not trigger Resume2 Flag Bit 7 The Resume2 Flag bit is a read only bit that indicates if a USB resume interrupt occu...

Page 53: ...upt triggered 0 Interrupt did not trigger SPI Registers There are 12 registers dedicated to SPI operation Each register is covered in this section and summarized in Table 33 SPI Configuration Register 0xC0C8 R W Figure 61 SPI Configuration Register Register Description The SPI Configuration register controls the SPI port Fields apply to both master and slave mode unless otherwise noted Table 33 SP...

Page 54: ... is active 0 Master state machine is idle Master Enable Bit 6 The Master Enable bit sets the SPI interface to master or slave This bit is only writable when the Master Active Enable bit reads 0 otherwise value will not change 1 Master SPI interface 0 Slave SPI interface SS Enable Bit 5 The SS Enable bit enables or disables the master SS output 1 Enable master SS output 0 Disable master SS output t...

Page 55: ...phase for a master mode transfer or set the slave to receive in slave mode 1 Initiates a read phase for a master transfer or sets a slave to receive In master mode this bit is sticky and remains set until the read transfer begins 0 Initiates the write phase for slave operation Transmit Ready Bit 9 The Transmit Ready bit is a read only bit that indicates if the transmit port is ready to empty and r...

Page 56: ... Figure 64 SPI Status Register Register Description The SPI Status register is a read only register that provides status for the SPI port FIFO Error Flag Bit 7 The FIFO Error Flag bit is a read only bit that indicates if a FIFO error occurred When this bit is set to 1 and the Transmit Empty bit of the SPI Control register is set to 1 then a Tx FIFO underflow has occurred Similarly when set with th...

Page 57: ... 0 No function Transfer Interrupt Clear Bit 0 The Transfer Interrupt Clear bit is a write only bit that will clear the block mode interrupt This bit is self clearing 1 Clear the block mode interrupt 0 No function Reserved All reserved bits must be written as 0 SPI CRC Control Register 0xC0D2 R W Figure 66 SPI CRC Control Register Register Description The SPI CRC Control register provides control o...

Page 58: ...not all ones 0 CRC value is all ones Reserved All reserved bits must be written as 0 SPI CRC Value Register 0xC0D4 R W Figure 67 SPI CRC Value Register Register Description The SPI CRC Value register contains the CRC value CRC Bits 15 0 The CRC field contains the SPI CRC In CRC Mode CRC7 the CRC value will be a seven bit value 6 0 Therefore bits 15 7 are invalid in CRC7 mode SPI Data Register 0xC0...

Page 59: ...5 0 The Address field sets the base address for the SPI transmit DMA SPI Transmit Count Register 0xC0DA R W Figure 70 SPI Transmit Count Register Register Description The SPI Transmit Count register designates the block byte length for the SPI transmit DMA transfer Count Bits 10 0 The Count field sets the count for the SPI transmit DMA transfer Reserved All reserved bits must be written as 0 Bit 1...

Page 60: ... receive DMA transfer Reserved All reserved bits must be written as 0 UART Registers There are three registers dedicated to UART operation Each of these registers is covered in this section and summarized in Table 36 Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W...

Page 61: ... use Reserved All reserved bits must be written as 0 UART Status Register 0xC0E2 R Figure 74 UART Status Register Register Description The UART Status register is a read only register that indicates the status of the UART buffer Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Reserved Scale Select Baud Select UART Enable Read Write R W R W R W ...

Page 62: ...egister to be transmitted This bit will automatically be cleared to 0 after the data is transmitted 1 Transmit buffer full transmit busy 0 Transmit buffer is empty and ready for a new byte of data UART Data Register 0xC0E4 R W Figure 75 UART Data Register Register Description The UART Data register contains data to be transmitted or received from the UART port Data written to this register will st...

Page 63: ...0xC006 This pin is also one of two possible GPIO wakeup sources G4 GPIO23 nRD IO GPIO23 General Purpose IO nRD HPI nRD H5 GPIO22 nWR IO GPIO22 General Purpose IO nWR HPI nWR G5 GPIO21 nCS IO GPIO21 General Purpose IO nCS HPI nCS nRESET A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 H1 H2 H3 H4 H5 H6 G1 G2 G3 G4 G5 G6 F1 F2 F3 F4 F5 F6 E1 E2 E3 E4 E5 E6 D1 D2 D3 D4 D5 D6 C1 C2 C3 C4 C5 C6 GPIO9 D9 nSSI Reserv...

Page 64: ...or HPI nSSI SPI nSSI C5 GPIO8 D8 MISO IO GPIO8 General Purpose IO D8 D8 for HPI MISO SPI MISO B5 GPIO7 D7 TX IO GPIO7 General Purpose IO D7 D7 for HPI TX UART TX Data is transmitted from this pin B4 GPIO6 D6 RX IO GPIO6 General Purpose IO D6 D6 for HPI RX UART RX Data is received on this pin C4 GPIO5 D5 IO GPIO5 General Purpose IO D5 D5 for HPI B3 GPIO4 D4 IO GPIO4 General Purpose IO D4 D4 for HPI...

Page 65: ...2 7V to 3 6V Ground Voltage 0V FOSC Oscillator or Crystal Frequency 12 MHz 500 ppm Parallel Resonant Crystal Requirements XTALIN XTALOUT A6 Reserved Tie to Gnd for normal operation F1 BOOSTVCC Power Booster Power Input 2 7V to 3 6V E2 VSWITCH Analog Output Booster Switching Output E1 BOOSTGND Ground Booster Ground C1 OTGVBUS Analog IO USB OTG Vbus D1 CSWITCHA Analog Charge Pump Capacitor D2 CSWITC...

Page 66: ...0 100 mA ICCB 7 8 Supply Current with Booster Enabled 2 transceivers powered 135 180 mA ISLEEP Sleep Current USB Peripheral includes 1 5K internal pull up 210 500 µA Without 1 5K internal pull up 5 30 µA ISLEEPB Sleep Current with Booster Enabled USB Peripheral includes 1 5K internal pull up 210 500 µA Without 1 5K internal pull up 5 30 µA Table 41 DC Characteristics Charge Pump Parameter Descript...

Page 67: ...B Device Session End 0 2 0 8 V E Efficiency When Loaded ILOAD 8 mA VCC 3 3V 75 RPD Data Line Pull Down 14 25 24 8 Ω RA_BUS_IN A device VBUS Input Impedance to GND VBUS is not being driven 40 100 kΩ RB_SRP_UP B device VBUS SRP Pull Up Pull up voltage 3 0V 281 Ω RB_SRP_DWN B device VBUS SRP Pull Down 656 Ω Table 41 DC Characteristics Charge Pump continued Parameter Description Conditions Min Typ Max...

Page 68: ...n Typical Max Unit fSCL Clock Frequency 400 kHz tLOW Clock Pulse Width Low 1300 ns tHIGH Clock Pulse Width High 600 ns tAA Clock Low to Data Out Valid 900 ns tBUF Bus Idle Before New Transmission 1300 ns tHD STA Start Hold Time 600 ns tSU STA Start Setup Time 600 ns tHD DAT Data In Hold Time 0 ns tSU DAT Data In Setup Time 100 ns tR Input Rise Time 300 ns tF Input Fall Time 300 ns tSU STO Stop Set...

Page 69: ...z Parameter Description Min Typical Max Unit tASU Address Setup 1 ns tAH Address Hold 1 ns tCSSU Chip Select Setup 1 ns tCSH Chip Select Hold 1 ns tDSU Data Setup 6 ns tWDH Write Data Hold 2 ns tWP Write Pulse Width 2 T 11 tCYC Write Cycle Time 6 T 11 nCS nRD nWR ADDR 1 0 Dout 15 0 tASU tWP tAH tCSSU tCSH tCYC tDSU tWDH Feedback ...

Page 70: ... tAH Address Hold 1 ns tCSSU Chip Select Setup 1 ns tCSH Chip Select Hold 1 ns tACC Data Access Time from HPI_nRD falling 1 T 11 tRDH Read Data Hold relative to the earlier of HPI_nRD rising or HPI_nCS rising 0 7 ns tRP Read Pulse Width 2 T 11 tCYC Read Cycle Time 6 T 11 tASU tRP tAH tCSSU tCSH tCYC tRDH tACC tRDH nCS nRD nWR ADDR 1 0 Din 15 0 Feedback ...

Page 71: ..._RATE value of 23 or higher BYTE mode received bytes are buffered in a FIFO The FIFO not empty condition becomes the RxRdy flag BLOCK mode received bytes are written directly to the memory system Bit 0 is LSB of data byte Data bits are HIGH true HSS_RxD HIGH data bit value 1 BT bit time 1 baud rate CPU may start another BYTE transmit right after TxRdy goes high start of last data bit to TxRdy high...

Page 72: ...y deasserting HSS_CTS at least 1 5T before HSS_RTS Transmission resumes when HSS_CTS returns HIGH HSS_CTS must remain HIGH until START bit HSS_RTS is deasserted in the third data bit time An application may choose to hold HSS_CTS until HSS_RTS is deasserted which always occurs after the START bit tCTSsetup tCTSsetup Start of transmission delayed until HSS_CTS goes high Start of transmission not de...

Page 73: ...ct Enable UD Reserved SAS Enable Mode Select 0000 0000 HSS Enable Reserved SPI Enable Reserved Interrupt 0 Polarity Select Interrupt 0 Enable 0000 0000 R W 0xC008 CPU Speed Reserved 0000 0000 Reserved CPU Speed 0000 000F R W 0xC00A Power Control Reserved Host Device 2 Wake Enable Reserved Host Device 1 Wake Enable OTG Wake Enable Reserved HSS Wake Enable SPI Wake Enable 0000 0000 HPI Wake Enable R...

Page 74: ...ble ISO Enable Reserved Arm Enable 0000 0000 R W 0xC082 0xC0A2 Host n Address Address 0000 0000 Address 0000 0000 R W 0xC084 0xC0A4 Host n Count Reserved Port Select Reserved Count 0000 0000 Count 0000 0000 R 0xC086 0xC0A6 Host n PID Reserved Overflow Flag Underflow Flag Reserved 0000 0000 Stall Flag NAK Flag Length Exception Flag Reserved Sequence Status Timeout Flag Error Flag ACK Flag 0000 0000...

Page 75: ...0 R W 0xC0B0 Host 2 Status Reserved SOF EOP Interrupt Flag Reserved xxxx xxxx Reserved Port A Wake Interrupt Flag Reserved Port A Con nect Change Interrupt Flag Reserved Port A SE0 Status Reserved Done Interrupt Flag xxxx xxxx R W 0xC0B0 Device 2 Status Reserved SOF EOP Timeout Interrupt Enable Wake Interrupt Flag SOF EOP Interrupt Flag Reset Interrupt Flag xxxx xxxx EP7 Interrupt Flag EP6 Interru...

Page 76: ...Reserved 0000 0000 Reserved Scale Select Baud Select UART Enable 0000 0111 R 0xC0E2 UART Status Reserved 0000 0000 Reserved Receive Full Transmit Full 0000 0000 R W 0xC0E4 UART Data Reserved 0000 0000 Data 0000 0000 R HPI Status Port VBUS Flag ID Flag Reserved SOF EOP2 Flag Reserved SOF EOP1 Flag Reset2 Flag Mailbox In Flag Resume2 Flag Resume1 Flag SIE2msg SIE1msg Done2 Flag Done1 Flag Reset1 Fla...

Page 77: ...of such use and in doing so indemnifies Cypress against all charges Ordering Information Package Diagram Purchase of I2 C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2 C Patent Rights to use these components in an I2 C system provided that the system conforms to the I2 C Standard Specification as defined by Philips EZ OTG is a tradema...

Page 78: ...B OTG Logo General Clean up F 472875 See ECN ARI Removed power consumption bullet from the Features bullet list Corrected number GPIO 31 20 to read GPIO 31 30 in Section Standalone Mode Made sentence into a Note in Section Reset Pin and repeated the note in Section Host Port Interface HPI Corrected the Host Device 1 Interrupt Enable Bit 8 Information in Section Interrupt Enable Register 0xC00E R W...

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