Document Number: 002-xxxxx Rev. **
Page 17 of 42
PRELIMINARY
CYBLE-013025-00
CYBLE-013030-00
ADC Port
The CYBLE-0130XX-00 contains a 16-bit ADC (effective number of bits is 10).
Additionally:
n
There are 9 analog input channels in the 32-pin package
n
The following GPIOs can be used as ADC inputs:
p
P0
p
P1
p
P8/P33 (select only one)
p
P11 on P11/P27 pin
p
P12 on P12/28 pin
p
P13/P28 (select only one)
p
P14/P38 (select only one)
p
P15
p
P32
n
The conversion time is 10 us.
n
There is a built-in reference with supply- or bandgap-based reference modes.
n
The maximum conversion rate is 187 kHz.
n
There is a rail-to-rail input swing.
The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes
the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input
multiplexers that select the ADC input signal V
inp
and the ADC reference signals V
ref
.
The ADC input range is selectable by firmware control:
n
When an input range of 0~3.6V is used, the input impedance is 3 MW.
n
When an input range of 0~2.4V is used, the input impedance is 1.84 MW.
n
When an input range of 0~1.2V is used, the input impedance is 680 kW.
ADC modes are defined in
.
Table 8. ADC Modes
Mode
ENOB (Typical)
Maximum Sampling Rate (kHz)
Latency
(u?s)
0
13
5.859
171
1
12.6
11.7
85
2
12
46.875
21
3
11.5
93.75
11
4
10
187
5
5. Settling time after switching channels. .
