Cypress EZ-BLE CYBLE-222014-01 Page 7 Manual Download | Manualshive

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CYBLE-222014-01

Document Number: 002-11186 Rev. *I

Page 6 of 39

Figure 1. Module Mechanical Drawing

Top View (View from Top)

Bottom View (Seen from Bottom)

Side View

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on

recommended host PCB layout, see

“Recommended Host PCB Layout”

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Summary of Contents for EZ-BLE CYBLE-222014-01

Page 1: ...ers as part of the Infineon product portfolio Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document Future revisions will occur when appropriate and any changes will be set out on the document history page Continuity of ordering part numbers Infineon continues to support existing pa...

Page 2: ...ed internal low speed oscillator ILO Two pin SWD for programming Power Consumption TX output power 18 dbm to 3 dbm Received signal strength indicator RSSI with 1 dB resolution TX current consumption of 15 6 mA radio only 0 dbm RX current consumption of 16 4 mA radio only Low power mode support Deep Sleep 1 3 µA with watch crystal oscillator WCO on Hibernate 150 nA with SRAM retention Stop 60 nA wi...

Page 3: ...Estimating Battery Life for BLE Applications AN85951 PSoC 4 CapSense Design Guide AN95089 PSoC 4 PRoC BLE Crystal Oscillator Selec tion and Tuning Techniques AN91445 Antenna Design and RF Layout Guidelines Technical Reference Manual TRM PRoC BLE Technical Reference Manual Knowledge Base Articles KBA212312 Pin Mapping Differences Between the EZ BLE CreatorEvaluationBoard CYBLE 222014 EVAL and the B...

Page 4: ...oth Low Energy Sub System BLESS hardware via the stack EZ Serial Bluetooth LE Firmware Platform The EZ Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed in Bluetooth LE applications EZ Serial implements an intuitive API protocol over the UART interface and exposes various status and control signals through the module s GPIOs making ...

Page 5: ...erals 20 Serial Communication 22 Memory 23 System Resources 23 Environmental Specifications 29 Environmental Compliance 29 RF Certification 29 Safety Certification 29 Environmental Conditions 29 ESD and EMI Protection 29 Regulatory Information 30 FCC 30 ISED 31 European R TTE Declaration of Conformity 31 MIC Japan 32 KC Korea 32 Packaging 33 Ordering Information 35 Part Numbering Convention 35 Acr...

Page 6: ...omponent area are maintained Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1 All dimensions are in millimeters mm Table 1 Module Design Dimensions See Figure 1 on page 6 for the mechanical reference drawing for CYBLE 222014 01 Dimension Item Specification Module dimensions Length X 10 00 0 15 mm Width Y 10 00 0 15 mm Antenna location dimensions Le...

Page 7: ...ing Top View View from Top Bottom View Seen from Bottom Side View Note 1 No metal should be located beneath or above the antenna area Only bare PCB material should be located beneath the antenna area For more information on recommended host PCB layout see Recommended Host PCB Layout on page 8 ...

Page 8: ... corner This placement minimizes the additional recommended keep out area stated in item 2 Refer to AN96841 for module placement best practices 2 To maximize RF performance the area immediately around the Cypress Bluetooth LE module chip antenna should contain an additional keep out area where no grounding or signal traces are contained The keep out area applies to all layers of the host board The...

Page 9: ...unless otherwise noted Pad length of 0 91 mm 0 455 mm from center of the pad on either side shown in Figure 6 is the minimum recommended host pad length The host PCB layout pattern can be completed using either Figure 4 Figure 5 or Figure 6 It is not necessary to use all figures to complete the host PCB layout pattern Figure 4 Host Layout Pattern for CYBLE 222014 01 Figure 5 Module Pad Location fr...

Page 10: ...ign mils 1 0 26 1 64 10 24 64 57 2 0 26 2 41 10 24 94 88 3 0 26 3 17 10 24 124 80 4 0 26 3 93 10 24 154 72 5 0 26 4 69 10 24 184 65 6 0 26 5 45 10 24 214 57 7 0 81 9 74 31 89 383 46 8 1 57 9 74 61 81 383 46 9 2 34 9 74 92 13 383 46 10 3 10 9 74 122 05 383 46 11 3 86 9 74 151 97 383 46 12 4 62 9 74 181 89 383 46 13 5 38 9 74 211 81 383 46 14 6 15 9 74 242 13 383 46 15 6 91 9 74 272 05 383 46 16 7 6...

Page 11: ... SCB0_SDA TCPWM 20 P1 5 SCB0_TX SCB0_MISO SCB0_SCL TCPWM 21 P3 6 SCB1_RTS TCPWM3_P 22 P4 0 8 SCB1_RTS SCB1_MOSI TCPWM0_P CMOD Notes 2 If the I2 S feature is used in the design the I2 S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator 3 TCPWM stands for timer counter and PWM If supported the pad can be configured to any of these peripheral functions 4 TCPWM connect...

Page 12: ...ct VDD and VDDR to the same supply 2 Independent supply Power VDD and VDDR separately External Component Recommendation In either connection scenario it is recommended to place an external ferrite bead between the supply and the module connection The ferrite bead should be positioned as close as possible to the module pin connection Figure 7 details the recommended host schematic options for a sin...

Page 13: ...CYBLE 222014 01 Document Number 002 11186 Rev I Page 12 of 39 The CYBLE 222014 01 schematic is shown in Figure 9 Figure 9 CYBLE 222014 01 Schematic Diagram ...

Page 14: ...et The Cypress module performance improves many of these characteristics For more information see Table 8 Table 6 Chip Antenna Specifications Component Reference Designator Description Silicon U1 76 pin WLCSP PSoC 4 Bluetooth LE Crystal Y1 24 000 MHz 10PF Crystal Y2 32 768 kHz 12 5PF Antenna E1 2 4 GHz 2 5 GHz chip antenna Item Description Chip Antenna Manufacturer Johanson Technology Inc Chip Ant...

Page 15: ...um IGPIO_ABS Maximum current per GPIO 25 25 mA Absolute maximum IGPIO_injection GPIO injection current Maximum for VIH VDD and minimum for VIL VSS 0 5 0 5 mA Absolute maximum current injected per pin LU Pin current for latch up 200 200 mA Parameter Description Min Typ Max Units Details Conditions RFO RF output power on ANT 18 0 3 dBm Configurable via register settings RXS RF receive sensitivity on...

Page 16: ...D 1 71 V to 1 89 V Regulator Bypassed IDD19 WDT with WCO on µA T 25 C IDD20 WDT with WCO on µA T 40 C to 85 C Hibernate Mode VDD 1 8 V to 3 6 V IDD27 GPIO and reset active 150 nA T 25 C VDD 3 3 V IDD28 GPIO and reset active nA T 40 C to 85 C Hibernate Mode VDD 3 6 V to 5 5 V IDD29 GPIO and reset active nA T 25 C VDD 5 V IDD30 GPIO and reset active nA T 40 C to 85 C Stop Mode VDD 1 8 V to 3 6 V IDD...

Page 17: ... 7 V 2 0 V VIL Input voltage LOW threshold 0 3 VDD V CMOS input LVTTL input VDD 2 7 V 0 3 VDD V LVTTL input VDD 2 7 V 0 8 V VOH Output voltage HIGH level VDD 0 6 V IOH 4 mA at 3 3 V VDD Output voltage HIGH level VDD 0 5 V IOH 1 mA at 1 8 V VDD VOL Output voltage LOW level 0 6 V IOL 8 mA at 3 3 V VDD Output voltage LOW level 0 6 V IOL 4 mA at 1 8 V VDD Output voltage LOW level 0 4 V IOL 3 mA at 3 3...

Page 18: ... 25 pF load 60 40 duty cycle FGPIOIN GPIO input operating frequency 1 71 V VDD 5 5 V 48 MHz 90 10 VIO Table 13 OVT GPIO DC Specifications P5_0 and P5_1 Only Parameter Description Min Typ Max Units Details Conditions IIL Input leakage absolute value VIH VDD 10 µA 25 C VDD 0 V VIH 3 0 V VOL Output voltage LOW level 0 4 V IOL 20 mA VDD 2 9 V Table 14 OVT GPIO AC Specifications P5_0 and P5_1 Only Para...

Page 19: ...n Min Typ Max Units Details Conditions A_RES Resolution 12 bits A_CHNIS_S Number of channels single ended 6 6 full speed 10 A CHNKS_D Number of channels differential 3 Diff inputs use neighboring I Os 10 A MONO Monotonicity Yes A_GAINERR Gain error 0 1 With external reference A_OFFSET Input offset voltage 2 mV Measured with 1 V VREF A_ISAR Current consumption 1 mA A_VINS Input voltage range single...

Page 20: ...dnl Differential nonlinearity VDD 1 71 V to 5 5 V 1 Msps 1 2 2 LSB VREF 1 V to VDD A_DNL Differential nonlinearity VDD 1 71 V to 3 6 V 1 Msps 1 2 LSB VREF 1 71 V to VDD A_DNL Differential nonlinearity VDD 1 71 V to 5 5 V 500 Ksps 1 2 2 LSB VREF 1 V to VDD A_THD Total harmonic distortion 65 dB FIN 10 kHz CSD Block Specifications Parameter Description Min Typ Max Units Details Conditions VCSD Voltag...

Page 21: ...WIDEXT Enable pulse width external 2 TCLK ns TTIMRESWINT Reset pulse width internal 2 TCLK ns TTIMRESEXT Reset pulse width external 2 TCLK ns Table 22 Counter DC Specifications Parameter Description Min Typ Max Units Details Conditions ICTR1 Block current consumption at 3 MHz 43 µA 16 bit counter ICTR2 Block current consumption at 12 MHz 152 µA 16 bit counter ICTR3 Block current consumption at 48 ...

Page 22: ... TPWMKILLEXT Kill pulse width external 2 TCLK ns TPWMEINT Enable pulse width internal 2 TCLK ns TPWMENEXT Enable pulse width external 2 TCLK ns TPWMRESWINT Reset pulse width internal 2 TCLK ns TPWMRESWEXT Reset pulse width external 2 TCLK ns Table 26 LCD Direct Drive DC Specifications Parameter Description Min Typ Max Units Details Conditions ILCDLOW Operating current in low power mode 17 5 µA 16 ...

Page 23: ...ter Description Min Typ Max Units Details Conditions ISPI1 Block current consumption at 1 Mbps 360 µA ISPI2 Block current consumption at 4 Mbps 560 µA ISPI3 Block current consumption at 8 Mbps 600 µA Table 33 Fixed SPI AC Specifications Parameter Description Min Typ Max Units Details Conditions FSPI SPI operating frequency master 6x over sampling 8 MHz Table 34 Fixed SPI Master Mode AC Specificati...

Page 24: ...C 10 K P E cycles 10 years Note 11 It can take as much as 20 ms to write to flash During this time the device should not be reset or flash operations will be interrupted and cannot be relied on to have completed Reset sources include the XRES pin software resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activ...

Page 25: ...001b 2 54 2 60 2 67 V VLVI11 LVI_A D_SEL 3 0 1010b 2 63 2 70 2 77 V VLVI12 LVI_A D_SEL 3 0 1011b 2 73 2 80 2 87 V VLVI13 LVI_A D_SEL 3 0 1100b 2 83 2 90 2 97 V VLVI14 LVI_A D_SEL 3 0 1101b 2 93 3 00 3 08 V VLVI15 LVI_A D_SEL 3 0 1110b 3 12 3 20 3 28 V VLVI16 LVI_A D_SEL 3 0 1111b 4 39 4 50 4 61 V LVI_IDD Block current 100 µA Table 43 Voltage Monitor AC Specifications Parameter Description Min Typ ...

Page 26: ...32 kHz 0 3 1 05 µA Table 48 ILO AC Specifications Parameter Description Min Typ Max Units Details Conditions TSTARTILO1 ILO startup time 2 ms FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Parameter Description Value Details Conditions ECOTRIM 24 MHz trim value firmware configuration 0x0000A0A0 Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Table 50 Blu...

Page 27: ...z 35 27 dBm RF PHY Specification RCV LE CA 04 C OBB3 Out of band blocking Wanted signal at 67 dBm and Interferer at F 2484 2997 MHz 35 27 dBm RF PHY Specification RCV LE CA 04 C OBB4 Out of band blocking Wanted signal a 67 dBm and Interferer at F 3000 12750 MHz 30 27 dBm RF PHY Specification RCV LE CA 04 C IMD Intermodulation performance Wanted signal at 64 dBm and 1 Mbps Bluetooth LE third fourth...

Page 28: ...in normal mode 18 7 mA IRX_RF Radio receive current in normal mode 16 4 mA Measured at VDDR IRX HIGHGAIN Receive current in high gain mode 21 5 mA ITX 3dBm TX current at 3 dBm setting PA10 20 mA ITX 0dBm TX current at 0 dBm setting PA7 16 5 mA ITX_RF 0dBm Radio TX current at 0 dBm setting PA7 15 6 mA Measured at VDDR ITX_RF 0dBm Radio TX current at 0 dBm excluding Balun loss 14 2 mA Guaranteed by ...

Page 29: ...luetooth LE TX transition time 120 140 µs IDLE2RX Bluetooth LE IDLE to Bluetooth LE RX transition time 75 120 µs RSSI Specifications RSSI ACC RSSI accuracy 5 dB RSSI RES RSSI resolution 1 dB RSSI PER RSSI sample period 6 µs Table 50 Bluetooth LE Subsystem continued Parameter Description Min Typ Max Units Details Conditions ...

Page 30: ...th LE module Table 51 Environmental Conditions for CYBLE 222014 01 ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference EMI A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection ...

Page 31: ...utlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help LABELING REQUIREMENTS The Original Equipment Manufacturer OEM must ensure that FCC labelling requirements are met This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this...

Page 32: ... Operation is subject to the following two conditions 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Cet appareil est conforme à la norme sur l innovation la science et le développement économique ISED norme RSS exempte de licence L exploitation est autorisée aux deux conditions suivant...

Page 33: ...h type certification number 203 JN0495 End products that integrate CYBLE 222014 01 do not need additional MIC Japan certification for the end product End product can display the certification label of the embedded module KC Korea CYBLE 222014 01 is certified for use in Korea with certificate number MSIP CRM Cyp 2005 ...

Page 34: ...orientation of the CYBLE 222014 01 in the tape as well as the direction for unreeling Figure 11 Component Orientation in Tape and Unreeling Direction Table 52 Solder Reflow Peak Temperature Module Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No of Cycles CYBLE 222014 01 22 pad SMT 260 C 30 seconds 2 Table 53 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 2 ...

Page 35: ...l dimensions used for the CYBLE 222014 01 Figure 12 Reel Dimensions The CYBLE 222014 01 is designed to be used with pick and place equipment in an SMT manufacturing environment The center of mass for the CYBLE 222014 01 is detailed in Figure 13 Figure 13 CYBLE 222014 01 Center of Mass ...

Page 36: ...r CPU Speed MHz Flash Size KB DMA CapSense SCB TCPWM 12 Bit SAR ADC I2 S LCD Package Packing CYBLE 222014 01 48 256 Yes Yes 2 4 1 Msps Yes Yes 22 SMT Tape and Reel Description Minimum Reel Quantity Maximum Reel Quantity Comments Reel Quantity 500 500 Ships in 500 unit reel quantities Minimum Order Quantity MOQ 500 Order Increment OI 500 U S Cypress Headquarters Address 198 Champion Court San Jose ...

Page 37: ...y Canada IDE integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications Japan PCB printed circuit board RX receive QDID qualification design ID SMT surface mount technology a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs TCPWM timer counter pulse width modulator PWM TUV Germany Technische...

Page 38: ...nnections Updated Table 4 Updated TCPWM column to add TCPWM capability on Port 2 pins Added Footnote 4 Completing Sunset Review D 5554670 12 15 2016 Updated Electrical Specification Updated SAR ADC Updated Table 18 to add Note 10 to specify under what conditions the maximum number of ADC channels can be achieved Completing Sunset Review E 5709580 04 24 2017 Updated the Cypress Logo and Copyright F...

Page 39: ...iption Updated description Updated hyperlinks Updated Two Easy To Use Design Environments to Get You Started Quickly Updated PSoC Creator Integrated Design Environment IDE Updated description Document History Page continued Document Title CYBLE 222014 01 EZ BLE Creator Module Document Number 002 11186 Revision ECN Submission Date Description of Change ...

Page 40: ... liability arising out of the application or use of any product or circuit described in this document Any information provided in this document including any sample design information or programming code is provided only for reference purposes It is the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of this infor...

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