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CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
DxCxxCR1 (Timer Control:000)
1,23h
13.3.8
DxCxxCR1 (Timer Control:000)
Digital Basic/Communication Type C Block Control Register 1
This register is the second Control register for a Timer, if the
register is configured as a ‘000’.
For additional information, refer to the
“Register Definitions” on page 348
in the Digital Blocks chapter.
7:4
Multi-Shot == 0
No Multi-shot function, and function will run repeatedly.
Multi-Shot > 0
Multi-shot number.
3
KILL_INV
0
Normal Kill signal
1
Invert Kill signal
2:1
KILL_MD[1:0]
KILL mode.
0Xb
NO KILL mode.
10b
"Kill Sync" mode: When the kill signal is asserted the DR0 Register is reloaded on every
block clock. The multi-shot counter is reloaded on the first rising edge of the block clock
after the kill signal is deasserted. This is also when the down counter starts counting again.
When the kill signal is asserted both digital block outputs are held low.
11b
"Kill Disable" mode: The block is immediately disabled when the kill signal is asserted. Both
block outputs are held low. The block must be restarted in firmware.
0
KILL_INT
0
Kill signal is not interrupt source
1
Kill signal is interrupt source and has highest priority
Individual Register Names and Addresses:
1,23h
DBC00CR1 : 1,23h
DBC01CR1 : 1,27h
DCC02CR1 : 1,2Bh
DCC03CR1 : 1,2Fh
DBC10CR1 : 1,33h
DBC11CR1 : 1,37h
DCC12CR1 : 1,3Bh
DCC13CR1 : 1,3Fh
DBC20CR1 : 1,43h
DBC21CR1 : 1,47h
DCC22CR1 : 1,4Bh
DCC23CR1 : 1,4Fh
7
6
5
4
3
2
1
0
Access : POR
RW : 0000
RW : 0 RW : 00 RW : 0
Bit Name
Multi-Shot KILL_INV
KILL_MD[1:0]
KILL_INT
Bit
Name
Description
Summary of Contents for CY8C28 series
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