MACx_CL1/ACCx_DR2
178
CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
0,AFh
13.2.49
MACx_CL1/ACCx_DR2
Accumulator Data Register 2
This is an accumulator clear register and the third byte of the accumulated value.
This register is only for PSoC devices with two MAC blocks. For additional information, refer to the
in the Multiply Accumulate chapter.
7:0
Data[7:0]
Read
Returns the third byte of the 32-bit accumulated value. The third byte is the next to most sig-
nificant byte for the accumulated value.
Write
Writing any value to this address will clear all four bytes of the Accumulator.
Individual Register Names and Addresses:
0,AFh
MAC1_CL1/ACC1_DR2 : 0,AFh
MAC0_CL1/ACC0_DR2 : 0,EFh
7
6
5
4
3
2
1
0
Access : POR
RW : 00
Bit Name
Data[7:0]
Bit
Name
Description
Summary of Contents for CY8C28 series
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