CapSense Performance Tuning with User Modules
CY8C20xx7/S CapSense
®
Design Guide
Doc. No. 001-78329 Rev. *E
47
4.4 Design Migration from CY8C20xx6A/AS to CY8C20xx7/S
The CY8C20xx7/S family of CapSense controllers provides superior noise immunity based on QuiteZone
TM
technology and improved sensitivity of 0.1 pF with a 5:1 SNR. This section summarizes key points to migrate an
existing CY8C20xx6A/AS design.
4.4.1 Discontinued Support/User Modules
The USB interface has been discontinued in the CY8C20xx7/S family.
On-chip debug (OCD) support has been discontinued for the CY8C20xx7/S family.
CSA and CSA_EMC user modules are not supported in the CY8C20xx7/S family.
4.4.2 Improvement and New Features
CSD-based improved CapSense sensing engine to provide an improved sensitivity of 0.1 pF.
New improved I
2
C slave interface (I2CSBUF User Module) with dedicated 32-byte buffer eliminating clock
stretching by the slave.
Improved I
2
C interface also supports wakeup interrupt from I
2
C slave address match event.
Use
2
C User Module for your design.
Table 4-8. I
2
C Features
System Requirements
I2CSBUF
EzI2Cs
I2CHW
I2Cm
Wake on I
2
C slave address match
Yes
Yes
No
N/A
Master requires clock stretch
No
Yes
Yes
N/A
I
2
C data buffer size
1-32 bytes
1-255 bytes
1-255 bytes
N/A
I
2
C master
No
No
No
Yes
4.4.3 Pin Compatibility
Table 4-9. Pin Compatibility
Package
Pin Compatibility to CY8C20xx6A/AS
16-SOIC
New package offering with CY8C20xx7/S
16-QFN
Pin to pin compatible
24-QFN
One pin - Pin 23 is Vss in CY8C20xx7/S while it is an I/O in CY8C20xx6A/AS
32-QFN
Two pins - Pin 28 is I/O and Pin 29 is Vss in CY8C20xx7/S; in CY8C20xx6A/AS, Pin 28 is Vss and Pin
29 is an I/O
30-WLCSP
Pin to pin compatible
48-QFN
Two pins - Pins 36 and 45 are NC while in CY8C20xx6A/AS both are I/O
