background image

2-Mbit (256K x 8) MoBL

®

 Static RAM

CY62138EV30

MoBL

®

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 38-05577 Rev. *A

 Revised February 14, 2006

Features

• Very high speed: 45 ns

— Wide voltage range: 2.20V – 3.60V

• Pin-compatible with CY62138CV30

• Ultra-low standby power

Typical standby current: 1 

µ

A

Maximum standby current: 7 

µ

A

Ultra-low active power

— Typical active current: 2 mA @ f = 1 MHz

• Easy memory expansion with CE

 

and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Offered in Pb-free 36-ball BGA package

Functional Description

[1]

The CY62138EV30 is a high-performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL

®

) in

portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE HIGH).

Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O

0

 through I/O

7

) is then written into the location

specified on the address pins (A

0

 through A

18

).

Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.

The eight input/output pins (I/O

0

 through I/O

7

) are placed in a

high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).

Note: 

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

A

1

COLUMN

DECODER

ROW DEC

O

D

E

R

SE

N

SE AM

PS

Data in Drivers

POWER

DOWN

WE

OE

I/O

0

I/O

1

I/O

2

I/O

3

256K x 8

ARRAY

I/O

7

I/O

6

I/O

5

I/O

4

A

0

A

12

CE

A

13

A

14

A

15

A

16

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

10

A

11

A

17

[+] Feedback 

Summary of Contents for CY62138EV30

Page 1: ...ly reduces power consumption The device can be put into standby mode reducing power consumption when deselected CE HIGH Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW Data on the eight I O pins I O0 through I O7 is then written into the location specified on the address pins A0 through A18 Reading from the device is accomplished by taking Chip Enable ...

Page 2: ... 3 Max Typ 3 Max CY62138EV30LL 2 2 3 0 3 6 45 2 2 5 15 20 1 7 Notes 2 NC pins are not connected on the die 3 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at VCC VCC typ TA 25 C A15 VCC A13 A12 A5 NC WE A7 I O4 I O5 A4 I O6 I O7 Vss A11 A10 A1 VSS I O0 A2 A8 A6 A3 A0 Vcc I O1 I O2 I O3 A17 NC A16 CE OE A9 A14 D E B A C F G H NC Top View...

Page 3: ... 0 4 V IOL 2 1 mA VCC 2 70V 0 4 V VIH Input HIGH Voltage VCC 2 2V to 2 7V 1 8 VCC 0 3V V VCC 2 7V to 3 6V 2 2 VCC 0 3V V VIL Input LOW Voltage VCC 2 2V to 2 7V 0 3 0 6 V VCC 2 7V to 3 6V 0 3 0 8 V IIX Input Leakage Current GND VI VCC 1 1 µA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 µA ICC VCC Operating Supply Current f fMAX 1 tRC VCC VCCmax IOUT 0 mA CMOS levels 15 20 mA f 1 MHz 2 ...

Page 4: ...nditions Min Typ 3 Max Unit VDR VCC for Data Retention 1 V ICCDR Data Retention Current VCC 1V CE VCC 0 2V VIN VCC 0 2V or VIN 0 2V 0 8 3 µA tCDR 7 Chip Deselect to Data Retention Time 0 ns tR 8 Operation Recovery Time tRC ns VCC VCC OUTPUT R2 30 pF INCLUDING JIG AND SCOPE GND 90 10 90 10 OUTPUT VTH Equivalent to THÉVENIN EQUIVALENT ALL INPUT PULSES RTH R1 Fall time 1 V ns Rise Time 1 V ns Data Re...

Page 5: ... Switching Waveforms Read Cycle No 1 Address Transition Controlled 13 14 Notes 9 Test Conditions for all parameters other than three state parameters assume signal transition time of 3 ns or less 1 V ns timing reference levels of VCC typ 2 input pulse levels of 0 to VCC typ and output loading of the specified IOL IOH as shown in the AC Test Loads and Waveforms section 10 At any given temperature a...

Page 6: ...ing this period the I Os are in output state and input signals should not be applied 18 If CE goes HIGH simultaneously with WE HIGH the output remains in high impedance state Switching Waveforms continued 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU DATA OUT HIGH IMPEDANCE IMPEDANCE ICC ISB tHZOE tHZCE tPD OE CE HIGH VCC SUPPLY CURRENT ADDRESS tHD tSD tPWE tSA tHA tAW tWC DATA I O ADDRESS CE WE ...

Page 7: ...VALID tAW tSA tPWE tHA tHD tSD tSCE CE ADDRESS WE DATA I O OE DATA I O ADDRESS tHD tSD tLZWE tSA tHA tAW tWC CE tHZWE DATAIN VALID NOTE 17 tPWE tSCE WE Truth Table CE WE OE Inputs Outputs Mode Power H X X High Z Deselect Power down Standby ISB L H L Data Out I O0 I O7 Read Active ICC L H H High Z Output Disabled Active ICC L L X Data in I O0 I O7 Write Active ICC Feedback ...

Page 8: ...ant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document may be the trademarks of their respective ...

Page 9: ...Typ value from 12 mA to 15 mA at f fmax 1 tRC Changed ISB1 and ISB2 Typ values from 0 7 µA to 1 µA and Max values from 2 5 µA to 7 µA Changed VCC stabilization time in footnote 7 from 100 µs to 200 µs Changed the AC test load capacitance from 50pF to 30pF on Page 4 Changed VDR from 1 5V to 1V on Page 4 Changed ICCDR from 1 µA to 3 µA in the Data Retention Characteristics table on Page 4 Corected t...

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