Cypress CY14B108L Specification Sheet Download Page 18

Page: 18 / 24

PRELIMINARY

CY14B108L, CY14B108N

Document #: 001-45523 Rev. *B

Page 18 of 24

CY14B108L-ZS45XCT

51-85087

44-pin TSOP II

Commercial

CY14B108L-ZS45XC

51-85087

44-pin TSOP II

CY14B108L-ZS45XIT

51-85087

44-pin TSOP II

Industrial

CY14B108L-ZS45XI

51-85087

44-pin TSOP II

CY14B108L-BA45XCT

51-85128

48-ball FBGA

Commercial

CY14B108L-BA45XC

51-85128

48-ball FBGA

CY14B108L-BA45XIT

51-85128

48-ball FBGA

Industrial

CY14B108L-BA45XI

51-85128

48-ball FBGA

CY14B108N-BA45XCT

51-85128

48-ball FBGA

Commercial

CY14B108N-BA45XC

51-85128

48-ball FBGA

CY14B108N-BA45XIT

51-85128

48-ball FBGA

Industrial

CY14B108N-BA45XI

51-85128

48-ball FBGA

CY14B108N-ZSP45XCT

51-85160

54-pin TSOP II

Commercial

CY14B108N-ZSP45XC

51-85160

54-pin TSOP II

CY14B108N-ZSP45XIT

51-85160

54-pin TSOP II

Industrial

CY14B108N-ZSP45XI

51-85160

54-pin TSOP II

All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.

Ordering Information

(continued)

Speed

(ns)

Ordering Code

Package

Diagram

Package Type

Operating

Range

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Summary of Contents for CY14B108L

Page 1: ...bits each The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data ...

Page 2: ...w x16 4 not to scale Notes 4 Address expansion for 16 Mbit NC pin not connected to die NC A8 NC NC VSS DQ6 DQ5 DQ4 VCC A13 DQ3 A12 DQ2 DQ1 DQ0 OE A9 CE NC A0 A1 A2 A3 A4 A5 A6 A11 A7 A14 A15 A16 A17 A18 A19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Top View not to scale A10 NC WE DQ7 HSB NC VSS VCC VCAP NC 4 54 TSOP I...

Page 3: ...OE Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles IO pins are tri stated on deasserting OE HIGH BHE Input Byte High Enable Active LOW Controls DQ15 DQ8 BLE Input Byte Low Enable Active LOW Controls DQ7 DQ0 VSS Ground Ground for the Device Must be connected to the ground of the system VCC Power Supply Power Supply Inputs to the Device HSB I...

Page 4: ... unique feature of QuantumTrap technology and is enabled by default on the CY14B108L CY14B108N During a normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part automatically disconnects the VCAP pin from VCC A STORE operati...

Page 5: ...erformed 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 Valid READ 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled reads or OE controlled reads After the sixth address in the sequence is entered the STORE cycle commences and the chip is disab...

Page 6: ...ata Output Data Output Data Output Data Active 6 L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z Active ICC2 6 L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output...

Page 7: ... inadvertent writes during power up or brown out conditions Noise Considerations Refer to CY application note AN1064 Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices The nonvolatile cells in this ...

Page 8: ...strial 75 75 57 mA mA mA ICC2 Average VCC Current during STORE All Inputs Don t Care VCC Max Average current for duration tSTORE 20 mA ICC3 7 AverageVCC Currentat tRC 200 ns 3V 25 C typical All I P cycling at CMOS levels Values obtained without output loads IOUT 0 mA 40 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Don t Care VCC Max Average current for duration tSTORE 10 mA ISB V...

Page 9: ...Capacitance TA 25 C f 1 MHz VCC 0 to 3 0V 14 pF COUT Output Capacitance 14 pF Thermal Resistance In the following table the thermal resistance parameters are listed 10 Parameter Description Test Conditions 48 FBGA 44 TSOP II 54 TSOP II Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA J...

Page 10: ...0 0 ns tHZBE 10 Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle tWC tWC Write Cycle Time 20 25 45 ns tPWE tWP Write Pulse Width 15 20 30 ns tSCE tCW Chip Enable To End of Write 15 20 30 ns tSD tDW Data Setup to End of Write 8 10 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tSA tAS Address Setup to Start of Write 0 0 0 ns tHA tWR ...

Page 11: ...ontrolled 3 14 15 16 Address Valid Address Data Output Output Data Valid Standby Active High Impedance CE OE BHE BLE ICC tHZCE tRC tACE tAA tLZCE tDOE tLZOE tDBE tLZBE tPU tPD tHZBE tHZOE DWD 2XWSXW DWD QSXW QSXW DWD 9DOLG LJK PSHGDQFH GGUHVV 9DOLG GGUHVV 3UHYLRXV DWD W W6 W W W W3 W6 W6 W W W Notes 16 CE or WE must be VIH during address transitions Feedback ...

Page 12: ... Figure 9 SRAM Write Cycle 3 BHE and BLE Controlled 3 14 15 16 Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSA tSCE tHA tBW tPWE Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSCE tSA tBW tHA tAW tPWE Feedback ...

Page 13: ... RECALL 20 VSWITCH VHDIS VVCCRISE tSTORE tSTORE tHHHD tHHHD tDELAY tDELAY tLZHSB tLZHSB tHRECALL tHRECALL HSB OUT Autostore POWER UP RECALL Read Write Inhibited RWI POWER UP RECALL Read Write BROWN OUT Autostore POWER UP RECALL Read Write POWER DOWN Autostore Note18 Note18 Note21 Notes 17 tHRECALL starts from the time VCC rises above VSWITCH 18 If an SRAM write has not taken place since the last n...

Page 14: ...uration 200 200 200 μs Switching Waveforms Figure 11 CE and OE Controlled Software STORE RECALL Cycle 23 Figure 12 Autostore Enable Disable Cycle tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY tSTORE tRECALL tHHHD tLZHSB High Impedance Address 1 Address 6 Address CE OE HSB STORE only DQ DATA RWI tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY Address 1 Address 6 Address CE O...

Page 15: ... tSTORE tHHHD tLZHSB Write latch set Write latch not set HSB IN HSB OUT DQ Data Out RWI HSB IN HSB OUT RWI HSB pin is driven high to VCC only by Internal SRAM is disabled as long as HSB IN is driven low HSB driver is disabled tDHSB 100kOhm resistor Address 1 Address 6 Address 1 Address 6 Soft Sequence Command tSS tSS CE Address VCC tSA tCW Soft Sequence Command tCW Notes 24 This is the amount of t...

Page 16: ...CE WE OE BHE 3 BLE 3 Inputs Outputs 2 Mode Power H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQ0 DQ15 Read Active L H L H L Data Out DQ0 DQ7 DQ8 DQ15 in High Z Read Active L H L L H Data Out DQ8 DQ15 DQ0 DQ7 in High Z Read Active L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disabl...

Page 17: ...XCT 51 85160 54 pin TSOP II Commercial CY14B108N ZSP20XC 51 85160 54 pin TSOP II CY14B108N ZSP20XIT 51 85160 54 pin TSOP II Industrial CY14B108N ZSP20XI 51 85160 54 pin TSOP II 25 CY14B108L ZS25XCT 51 85087 44 pin TSOP II Commercial CY14B108L ZS25XC 51 85087 44 pin TSOP II CY14B108L ZS25XIT 51 85087 44 pin TSOP II Industrial CY14B108L ZS25XI 51 85087 44 pin TSOP II CY14B108L BA25XCT 51 85128 48 ba...

Page 18: ...GA CY14B108N BA45XCT 51 85128 48 ball FBGA Commercial CY14B108N BA45XC 51 85128 48 ball FBGA CY14B108N BA45XIT 51 85128 48 ball FBGA Industrial CY14B108N BA45XI 51 85128 48 ball FBGA CY14B108N ZSP45XCT 51 85160 54 pin TSOP II Commercial CY14B108N ZSP45XC 51 85160 54 pin TSOP II CY14B108N ZSP45XIT 51 85160 54 pin TSOP II Industrial CY14B108N ZSP45XI 51 85160 54 pin TSOP II All parts are Pb free The...

Page 19: ...l Blank Std Speed 20 20 ns 25 25 ns Data Bus L x8 N x16 Density 108 8 Mb Voltage B 3 0V Cypress CY 14 B 108L ZS P 20 X C T NVSRAM 14 Auto Store Software STORE Hardware STORE Temperature C Commercial 0 to 70 C I Industrial 40 to 85 C Pb Free Package BA 48 FBGA ZS TSOP II 45 45 ns P 54 Pin Blank 44 Pin 48 Ball Feedback ...

Page 20: ...0 PLANE SEATING PIN 1 I D 44 1 18 517 0 729 0 800 BSC 0 5 0 400 0 016 0 300 0 012 EJECTOR PIN R G O K E A X S 11 735 0 462 10 058 0 396 10 262 0 404 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 0 0315 18 313 0 721 10 058 0 396 10 262 0 404 0 597 0 0235 0 406 0 0160 0 210 0 0083 0 120 0 0047 BASE PLANE 0 10 004 22 23 TOP VIEW BOTTOM VIEW 51 85087 A Feedback ...

Page 21: ...ge Diagrams continued A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 20 MAX C SEATING PLANE 0 53 0 05 0 25 C 0 15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 10 00 0 10 A 10 00 0 10 6 00 0 10 B 1 875 2 625 0 36 51 85128 D Feedback ...

Page 22: ...PRELIMINARY CY14B108L CY14B108N Document 001 45523 Rev B Page 22 of 24 Figure 17 54 Pin TSOP II 51 85160 Package Diagrams continued 51 85160 Feedback ...

Page 23: ...76670 GVCH PYRS 03 20 2009 Added maximum accumulated storage time for 150 C and 85 C Temperature Added best practices Changed ICC2 from 12mA to 20mA Changed ICC3 from 38mA to 40mA Changed ICC4 from 12mA to 10mA Changed ISB from 6mA to 10mA Changed VCAP from 164uF to 360uF Changed Input Rise and Fall Times from 5ns to 3ns Updated ICC1 ICC3 ISBand IOZ Test conditions Changed tDELAY to 20ns 25ns 25ns...

Page 24: ... and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPL...

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