Cypress CY14B104K Specification Sheet Download Page 10

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PRELIMINARY

CY14B104K, CY14B104M

Document #: 001-07103 Rev. *K

Page 10 of 31

Table 4. RTC Register Map

[8]

Register

BCD Format Data

[9]

Function/Range

CY14B104K CY14B104M

0x7FFFF

0x3FFFF

10s Years

Years

Years: 00–99

0x7FFFE

0x3FFFE

10s

Months

Months: 01–12

0x7FFFD

0x3FFFD

10s Day of Month

Day Of Month

Day of Month: 01–31

0x7FFFC

0x3FFFC

Day of week

Day of week: 01–07

0x7FFFB

0x3FFFB

10s Hours

Hours

Hours: 00–23

0x7FFFA

0x3FFFA

10s Minutes

Minutes

Minutes: 00–59

0x7FFF9

0x3FFF9

10s Seconds

Seconds

Seconds: 00–59

0x7FFF8

0x3FFF8

OSCEN

(0)

Cal Sign

(0)

Calibration (00000)

Calibration Values

[10]

0x7FFF7

0x3FFF7

WDS

(0)

WDW (0)

WDT (000000)

Watchdog

[10]

0x7FFF6

0x3FFF6

WIE (0)

AIE (0)

PFE (0)

H/L

(1)

P/L (0)

Interrupts

[10]

0x7FFF5

0x3FFF5

M (1)

10s Alarm Date

Alarm Day

Alarm, Day of Month:

01–31

0x7FFF4

0x3FFF4

M (1)

10s Alarm Hours

Alarm Hours

Alarm, Hours: 00–23

0x7FFF3

0x3FFF3

M (1)

10 Alarm Minutes

Alarm Minutes

Alarm, Minutes:

00–59

0x7FFF2

0x3FFF2

M (1)

10 Alarm Seconds

Alarm, Seconds

Alarm, Seconds:

00–59

0x7FFF1

0x3FFF1

10s Centuries

Centuries

Centuries: 00–99

0x7FFF0

0x3FFF0

WDF

OSCF

CAL (0)

W (0)

R (0)

Flags

[10]

Note

8. Upper Byte D

-D

(CY14B104MA) of RTC registers are reserved for future use

9. ( ) designates values shipped from the factory.
10. This is a binary value, not a BCD value.

[+] Feedback

Summary of Contents for CY14B104K

Page 1: ...tic RAM with a full featured Real Time Clock in a monolithic integrated circuit The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM is read and written infinite number of times while independent nonvolatile data resides in the nonvolatile elements The Real Time Clock function provides an accurate clock with leap year ...

Page 2: ...High Enable Active LOW Controls DQ15 DQ8 BLE Input Byte Low Enable Active LOW Controls DQ7 DQ0 X1 Output Crystal Connection Drives crystal on start up X2 Input Crystal Connection For 32 768 KHz crystal VRTCcap Power Supply Capacitor Supplied Backup RTC Supply Voltage Left unconnected if VRTCbat is used VRTCbat Power Supply Battery Supplied Backup RTC Supply Voltage Left unconnected if VRTCcap is u...

Page 3: ...it words Keep OE HIGH during the entire write cycle to avoid data bus contention on common I O lines If OE is left LOW internal circuitry turns off the output buffers tHZWE after WE goes LOW AutoStore Operation The CY14B104K CY14B104M stores data to the nvSRAM using one of three storage operations These three operations are Hardware STORE activated by the HSB Software STORE activated by an address...

Page 4: ...pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The CY14B104K CY14B104M Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order During the STORE cycle an erase of the previ...

Page 5: ... through subsequent power down cycles The part comes from the factory with AutoStore enabled Table 2 Mode Selection CE WE OE BHE BLE 3 A15 A0 6 Mode I O Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output D...

Page 6: ...ten to the read bit R all RTC registers are simultaneously updated within 20 ms Setting the Clock Setting the write bit W in the flags register at 0x7FFF0 to a 1 stops updates to the time keeping registers and enables the time to be set The correct day date and time is then written into the registers and must be in 24 hour BCD format The time written is referred to as the Base Time This value is s...

Page 7: ...for every 125 829 120 actual oscillator cycles that is 4 068 or 2 034 ppm of adjustment per calibration step in the Calibration register To determine the required calibration the CAL bit in the Flags register 0x7FFF0 must be set to 1 This causes the INT pin to toggle at a nominal frequency of 512 Hz Any deviation measured from the 512 Hz indicates the degree and direction of the required correctio...

Page 8: ...sed to drive level or pulse mode output from the INT pin In pulse mode the pulse width is internally fixed at approximately 200 ms This mode is intended to reset a host microcontroller In the level mode the pin goes to its active polarity until the Flags register is read by the user This mode is used as an interrupt to a host microcontroller The control bits are summarized in the following section...

Page 9: ... 6 pF C1 21 pF C2 21 pF X1 X2 Y1 C2 C1 Note The recommended values for C1 and C2 include board trace capacitance Watchdog Timer Power Monitor Clock Alarm VINT WDF WIE PF PFE AF AIE P L Pin Driver H L INT VCC VSS WDF Watchdog Timer Flag WIE Watchdog Interrupt PF Power Fail Flag PFE Power Fail Enable AF Alarm Flag AIE Alarm Interrupt Enable P L Pulse Level H L High Low Enable Feedback ...

Page 10: ...7FFF8 0x3FFF8 OSCEN 0 0 Cal Sign 0 Calibration 00000 Calibration Values 10 0x7FFF7 0x3FFF7 WDS 0 WDW 0 WDT 000000 Watchdog 10 0x7FFF6 0x3FFF6 WIE 0 AIE 0 PFE 0 0 H L 1 P L 0 0 0 Interrupts 10 0x7FFF5 0x3FFF5 M 1 0 10s Alarm Date Alarm Day Alarm Day of Month 01 31 0x7FFF4 0x3FFF4 M 1 0 10s Alarm Hours Alarm Hours Alarm Hours 00 23 0x7FFF3 0x3FFF3 M 1 10 Alarm Minutes Alarm Minutes Alarm Minutes 00 ...

Page 11: ...automatically adjusted for 0x7FFFC 0x3FFFC Time Keeping Day D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Day of Week Lower nibble three bits contains a value that correlates to day of the week Day of the week is a ring counter that counts from 1 to 7 then returns to 1 The user must assign meaning to the day value because the day is not integrated with the date 0x7FFFB 0x3FFFB Time Keeping Hours D7 D6 D5 D4 D...

Page 12: ...ltiplier of the 32 Hz count 31 25 ms The range of timeout value is 31 25 ms a setting of 1 to 2 seconds setting of 3 Fh Setting the watchdog timer register to 0 disables the timer These bits can be written only if the WDW bit was set to 0 on a previous cycle 0x7FFF6 0x3FFF6 Interrupt Status Control D7 D6 D5 D4 D3 D2 D1 D0 WIE AIE PFE 0 H L P L 0 0 WIE Watchdog Interrupt Enable When set to 1 and a ...

Page 13: ...chdog timer is allowed to reach 0 without being reset by the user It is cleared to 0 when the Flags register is read or on power up AF Alarm Flag This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits 0 It is cleared when the Flags register is read or on power up PF Power Fail Flag This read only bit is set to 1 when power falls bel...

Page 14: ...ustrial 70 70 52 mA mA ICC2 Average VCC Current during STORE All Inputs Don t Care VCC Max Average current for duration tSTORE 10 mA ICC3 11 Average VCC Current at tRC 200 ns 3V 25 C typical All I P cycling at CMOS levels Values obtained without output loads IOUT 0 mA 35 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Don t Care VCC Max Average current for duration tSTORE 5 mA ISB V...

Page 15: ...Unit CIN Input Capacitance TA 25 C f 1 MHz VCC 0 to 3 0V 7 pF COUT Output Capacitance 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed 14 Parameter Description Test Conditions 44 TSOP II 54 TSOP II Unit ΘJA Thermal Resistance Junction to Ambient Testconditionsfollowstandard test methods and procedures for measuring thermal impedance in accordance with EIA...

Page 16: ...scription Test Conditions Min Typ Max Units IBAK 15 RTC Backup Current Room Temperature 25o C 300 nA Hot Temperature 85o C 450 nA VRTCbat RTC Battery Pin Voltage 1 8 3 0 3 3 V VRTCcap RTC Capacitor Pin Voltage 1 5 3 0 3 6 V tOCS RTC Oscillator Time to Start 1 2 sec Notes 15 From either VRTCcap or VRTCbat Feedback ...

Page 17: ...0 0 ns tHZBE 14 Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle tWC tWC Write Cycle Time 20 25 45 ns tPWE tWP Write Pulse Width 15 20 30 ns tSCE tCW Chip Enable To End of Write 15 20 30 ns tSD tDW Data Setup to End of Write 8 10 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tSA tAS Address Setup to Start of Write 0 0 0 ns tHA tWR ...

Page 18: ... 21 Address Valid Address Data Output Output Data Valid Standby Active High Impedance CE OE BHE BLE ICC tHZCE tRC tACE tAA tLZCE tDOE tLZOE tDBE tLZBE tPU tPD tHZBE tHZOE Data Output Data Input Input Data Valid High Impedance Address Valid Address Previous Data tWC tSCE tHA tBW tAW tPWE tSA tSD tHD tHZWE tLZWE WE BHE BLE CE Notes 21 CE or WE must be VIH during address transitions Feedback ...

Page 19: ...ut Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSA tSCE tHA tBW tPWE Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSCE tSA tBW tHA tAW tPWE Not applicable for RTC register writes Note 22 Only CE and WE controlled writes to RTC registers are allowed BLE pin must be held LOW before CE or WE pin goes LOW for...

Page 20: ... RECALL 26 VSWITCH VHDIS VVCCRISE tSTORE tSTORE tHHHD tHHHD tDELAY tDELAY tLZHSB tLZHSB tHRECALL tHRECALL HSB OUT Autostore POWER UP RECALL Read Write Inhibited RWI POWER UP RECALL Read Write BROWN OUT Autostore POWER UP RECALL Read Write POWER DOWN Autostore Note24 Note24 Note27 Notes 23 tHRECALL starts from the time VCC rises above VSWITCH 24 If an SRAM write has not taken place since the last n...

Page 21: ...9 Figure 14 Autostore Enable and Disable Cycle tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY tSTORE tRECALL tHHHD tLZHSB High Impedance Address 1 Address 6 Address CE OE HSB STORE only DQ DATA RWI tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY Address 1 Address 6 Address CE OE DQ DATA tSS Notes 28 The software sequence is clocked with CE controlled or OE controlled reads 2...

Page 22: ...latch set Write latch not set HSB IN HSB OUT DQ Data Out RWI HSB IN HSB OUT RWI HSB pin is driven high to VCC only by Internal SRAM is disabled as long as HSB IN is driven low HSB driver is disabled tDHSB 100kOhm resistor Address 1 Address 6 Address 1 Address 6 Soft Sequence Command tSS tSS CE Address VCC tSA tCW Soft Sequence Command tCW Notes 32 This is the amount of time it takes to take action...

Page 23: ...n CE WE OE BHE BLE Inputs and Outputs 2 Mode Power H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQ0 DQ15 Read Active L H L H L Data Out DQ0 DQ7 DQ8 DQ15 in High Z Read Active L H L L H Data Out DQ8 DQ15 DQ0 DQ7 in High Z Read Active L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disa...

Page 24: ...pe Reel Blank Std Speed 20 20 ns 25 25 ns Data Bus K x8 RTC M x16 RTC Density 104 4 Mb Voltage B 3 0V Cypress CY14 B 104 K ZS P 20 X C T NVSRAM 14 AutoStore Software STORE Hardware STORE Temperature C Commercial 0 to 70 C I Industrial 40 to 85 C Pb Free Package ZS TSOP II P 54 Pin Blank 44 Pin 45 45 ns Feedback ...

Page 25: ...OPII CY14B104K ZS25XIT 51 85087 44 pin TSOPII Industrial CY14B104K ZS25XI 51 85187 44 pin TSOPII CY14B104M ZSP25XCT 51 85160 54 pin TSOPII Commercial CY14B104M ZSP25XC 51 85160 54 pin TSOPII CY14B104M ZSP25XIT 51 85160 54 pin TSOPII Industrial CY14B104M ZSP25XI 51 85160 54 pin TSOPII 45 CY14B104K ZS45XCT 51 85087 44 pin TSOPII Commercial CY14B104K ZS45XC 51 85087 44 pin TSOPII CY14B104K ZS45XIT 51...

Page 26: ...0 PLANE SEATING PIN 1 I D 44 1 18 517 0 729 0 800 BSC 0 5 0 400 0 016 0 300 0 012 EJECTOR PIN R G O K E A X S 11 735 0 462 10 058 0 396 10 262 0 404 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 0 0315 18 313 0 721 10 058 0 396 10 262 0 404 0 597 0 0235 0 406 0 0160 0 210 0 0083 0 120 0 0047 BASE PLANE 0 10 004 22 23 TOP VIEW BOTTOM VIEW 51 85087 A Feedback ...

Page 27: ...PRELIMINARY CY14B104K CY14B104M Document 001 07103 Rev K Page 27 of 31 Figure 18 54 Pin TSOP II 51 85160 Package Diagrams continued 51 85160 Feedback ...

Page 28: ...ue in DC table Added 44 TSOP II in Thermal Resistance table Modified part nomenclature table Changes reflected in the ordering information table C 517793 See ECN TUP Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35μF Changed VIH max to Vcc 0 5V Changed tSTORE to 15ns Changed tPWE to 10ns Changed tSCE to 15ns Chan...

Page 29: ...d ISB from 2mA to 3mA Added input leakage current IIX for HSB in DC Electrical Characteristics table Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value Corrected typo in tDBE value from 22ns to 20ns for 45ns part Corrected typo in tHZBE value from 22ns to 15ns for 45ns part Corrected typo in tAW value from 15ns to 10ns for 15ns part Changed Vrtccap max from 2 7V to 3 6V C...

Page 30: ...igure 4 Removed RF register and Changed C2 value from 56pF to 12pF Updated Register Map Table 3 Updated Register map detail Table 4 Maximum Ratings Added Max Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed ICC2 from 6mA to 10mA Changed ICC4 from 6mA to 5mA Changed ISB from 3mA to 5mA Updated ICC1 ICC3 ISB and IOZ Test conditions Changed VCA...

Page 31: ...KES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described here...

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