Cypress Semiconductor West Bridge Astoria AN46860 Checklist Download Page 4

AN46860 

 
 

December 12, 2008 

Document No. 001-46860 Rev. *A 

Document History 

Document Title: Schematic Review Checklist for West Bridge

®

 

Astoria™ 

Document Number: 001-46860 

Revision 

ECN 

Submission 

Date 

Orig. of 

Change 

Description of Change 

** 

2516790 

06/16/2008 

PRKU 

New application note. 

*A 

2620808 

12/12/2008 

OSG/AESA 

Numbered the paragraphs for better readability and  added another point in 
both P-port and S-port sections. Changed title to 

“Schematic Review Checklist 

for West Bridge® 

Astoria™”. 

 
 
 
 
 
 
 
 
 

 

 
 
 
 
 

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Summary of Contents for West Bridge Astoria AN46860

Page 1: ...rocessor interface 3 The DRQ Status Register and DRQ Mask Register indicate the available endpoints for transfer They must be accessed even if a DMA or burst operation is not being implemented on the P port interface Use the DRQ or the INT signal to indicate to the processor that at least one of the bits in the DRQ Status Register is set If INT is used an extra read of the P port Interrupt Registe...

Page 2: ... speed mode Table 3 Frequency vs Trace Length SD Default Mode SDFREQ MHz Maximum Trace Length in 24 00 1 94 21 82 7 55 20 00 13 17 18 46 18 78 17 14 24 4 Table 4 lists the acceptable frequencies for Astoria and the corresponding maximum trace lengths for SD cards that are capable of operating in high speed mode Table 4 Frequency vs Trace Length SD High Speed Mode SDFREQ MHz Maximum Trace Length in...

Page 3: ...rately with 0 01 µF and 0 1 µF capacitors 3 UVDDQ requires 2 2 µF and 0 1 µF decoupling 4 GVDDQ PVDDQ SSVDDQ SNVDDQ and XVDDQ do not have any specific decoupling requirements Combine them with the decoupling for other supplies at the same level If in doubt use 2 2 µF and 0 1 µF Miscellaneous All unused output only pins may be left floating but do not leave unused input only and input output pins f...

Page 4: ...mes all risk of such use and in doing so indemnifies Cypress against all charges This Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transf...

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