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Cypress Semiconductor STK14C88-5, Specification Sheet, Page: 13 / 17

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Cypress Semiconductor STK14C88-5 Specification Sheet Download Page 13

STK14C88-5

Document Number: 001-51038 Rev. **

Page 13 of 17

Hardware STORE Cycle

Parameter

Alt

Description

STK14C88-5

Unit

Min

Max

t

DHSB 

[16, 20]

t

RECOVER, 

t

HHQX

Hardware STORE High to Inhibit Off

700

ns

t

PHSB

t

HLHX

Hardware STORE Pulse Width

15

ns

t

HLBL

Hardware STORE Low to STORE Busy

300

ns

Switching Waveforms

Figure 14.  Hardware STORE Cycle

Note

20. t

DHSB 

is only applicable after t

STORE

 is complete.

[+] Feedback 

Summary of Contents for STK14C88-5

Page 1: ...nvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at...

Page 2: ...utput Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS Ground Ground for the Device The device is connected to ground of the system VCC Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulle...

Page 3: ...3 AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK14C88 5 During normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part automatically dis...

Page 4: ...8 5 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements When a STORE cycle is initiated input and output are disabled until the cycle is completed Because a sequence of READs from spe...

Page 5: ...ly initiated by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the STK14C88 5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 5 and Figure 6 shows the relationship between ICC and READ or WRITE cycle time Worst case current consumption is shown for both CMOS and TTL input lev...

Page 6: ... to meet this requirementandnotexceedthe maximumVCAP valuebecause the higher inrush currents may reduce the reliability of the internal pass transistor Customers that want to use a larger VCAP value to make sure there is extra store charge should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period Table 1 Hardware Mode Se...

Page 7: ...e Values obtained without output loads 10 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Do Not Care VCC Max Average current for duration tSTORE 2 mA ISB1 7 VCC Standby Current Standby Cycling TTL Input Levels tRC 35 ns CE VIH tRC 45 ns CE VIH 26 23 mA mA ISB2 7 VCC Standby Current CE VCC 0 2V All others VIN 0 2V or VCC 0 2V Standby current level after nonvolatile cycle is complete...

Page 8: ...ion Test Conditions 32 CDIP 32 LCC Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W Figure 7 AC Test Loads AC Test Conditions 5 0V Output 30 pF R1 963Ω R2 512Ω 5 0V Output 5 pF R1 963Ω R2 512Ω For Tri state Specs Input Pulse Level...

Page 9: ...5 5 ns tHZCE 11 tEHQZ Chip Disable to Output Inactive 13 15 ns tLZOE 11 tGLQX Output Enable to Output Active 0 0 ns tHZOE 11 tGHQZ Output Disable to Output Inactive 13 15 ns tPU 8 tELICCH Chip Enable to Power Active 0 0 ns tPD 8 tEHICCL Chip Disable to Power Standby 35 45 ns Switching Waveforms Figure 8 SRAM Read Cycle 1 Address Controlled 9 10 Figure 9 SRAM Read Cycle 2 CE and OE Controlled 9 W5 ...

Page 10: ... tHA tWHAX tEHAX Address Hold After End of Write 0 0 ns tHZWE 11 12 tWLQZ Write Enable to Output Disable 13 15 ns tLZWE 11 tWHQX Output Active After End of Write 5 5 ns Switching Waveforms Figure 10 SRAM Write Cycle 1 WE Controlled 13 14 Figure 11 SRAM Write Cycle 2 CE Controlled 13 14 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMPEDANCE PREVIOUS D...

Page 11: ...Voltage Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 6 V tVCCRISE VCC Rise Time 150 μs tVSBL 13 Low Voltage Trigger VSWITCH to HSB low 300 ns Switching Waveforms Figure 12 AutoStore Power Up RECALL WE Notes 15 tHRECALL starts from the time VCC rises above VSWITCH 16 CE and OE low and WE high for output behavior 17 HSB is asserted low for 1us when VCAP drops through VSWITCH If an SRAM W...

Page 12: ...E 18 19 tELAX Address Hold Time 20 20 ns tRECALL RECALL Duration 20 20 μs Switching Waveforms Figure 13 CE Controlled Software STORE RECALL Cycle 19 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 18 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts the sequen...

Page 13: ... STK14C88 5 Unit Min Max tDHSB 16 20 tRECOVER tHHQX Hardware STORE High to Inhibit Off 700 ns tPHSB tHLHX Hardware STORE Pulse Width 15 ns tHLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveforms Figure 14 Hardware STORE Cycle Note 20 tDHSB is only applicable after tSTORE is complete Feedback ...

Page 14: ...4 32 pin CDIP 300 mil STK14C88 5K45M 001 51694 32 pin CDIP 300 mil STK14C88 5L45M 51 80068 32 pin LCC 450mil The above table contains Final information Please contact your local Cypress sales representative for availability of these parts Speed 35 35 ns 45 45 ns Package C Ceramic 32 pin 300 mil DIP Part Numbering Nomenclature STK14C88 5 C 35 M Temperature Range M Military 55 to 125 C K L Ceramic 3...

Page 15: ...STK14C88 5 Document Number 001 51038 Rev Page 15 of 17 Package Diagram Figure 15 32 Pin 300 Mil Side Braze DIL 001 51694 001 51694 Feedback ...

Page 16: ...STK14C88 5 Document Number 001 51038 Rev Page 16 of 17 Figure 16 32 Pad 450 Mil LCC 51 80068 Package Diagram continued 51 80068 Feedback ...

Page 17: ...specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ...

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