Cypress Semiconductor STK11C68 Specification Sheet Download Page 11

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STK11C68

Document Number: 001-50638 Rev. **

Page 11 of 16

Ordering Information

Speed (ns)

Ordering Code

Package Diagram

Package Type

Operating Range

STK11C68-SF25TR

001-85058

28-Pin SOIC (330 mil)

Commercial

STK11C68-SF25

001-85058

28-Pin SOIC (330 mil)

STK11C68-SF25ITR

001-85058

28-Pin SOIC (330 mil)

Industrial

STK11C68-SF25I

001-85058

28-Pin SOIC (330 mil)

STK11C68-SF35TR

001-85058

28-Pin SOIC (330 mil)

Commercial

STK11C68-SF35

001-85058

28-Pin SOIC (330 mil)

STK11C68-C35

001-51695

28-Pin CDIP (300 mil)

STK11C68-L35

001-51696

28-Pin LCC (350 mil)

STK11C68-SF35ITR

001-85058

28-Pin SOIC (330 mil)

Industrial

STK11C68-SF35I

001-85058

28-Pin SOIC (330 mil)

STK11C68-C35I

001-51695

28-Pin CDIP (300 mil)

STK11C68-L35I

001-51696

28-Pin LCC (350 mil)

Part Numbering Nomenclature

Packaging Option:
TR = Tape and Reel
Blank = Tube

Speed:
25 - 25 ns
35 - 35 ns

Package:
S = Plastic 28-pin 330 mil SOIC

STK11C68 - S F 45 I TR

Temperature Range:

Blank - Commercial (0 to 70°C)

C = Ceramic 28-pin 300 mil DIP

L = Ceramic 28-pin 350 mil LLC

Lead Finish

F = 100% Sn (Matte Tin)

45 - 45 ns

I - Industrial (-40 to 85°C)

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Summary of Contents for STK11C68

Page 1: ...tatic RAM with a nonvol atile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers under software control from SRAM to the nonvolatile elements the STORE...

Page 2: ...ut Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS Gr...

Page 3: ...software sequence is clocked with CE controlled Reads When the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled It is important that Read cycles and not Write cycles are used in the sequence It is not necessary that OE is LOW for a valid sequence After the tSTORE cycle time is fulfilled the SRAM is again activated for Read and Write operation Software REC...

Page 4: ...atus and so on must always program a unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system manufacturing test to ensure these system routines work consistently Power up boot firmware routines should rewrite the nvSRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM i...

Page 5: ...nputs Do Not Care VCC Max Average current for duration tSTORE 3 mA ICC3 Average VCC Current at tRC 200 ns 5V 25 C Typical WE VCC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 10 mA ISB1 2 VCC Standby Current Standby Cycling TTL Input Levels tRC 25 ns CE VIH tRC 35 ns CE VIH tRC 45 ns CE VIH Commercial 27 23 20 mA mA mA Industrial 28 2...

Page 6: ...rameter Description Test Conditions 28 SOIC 28 CDIP 28 LCC Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD TBD C W Figure 4 AC Test Loads AC Test Conditions 5 0V Output 30 pF R1 480Ω R2 255Ω Input Pulse Levels 0V to 3V Input Rise...

Page 7: ... 5 5 5 ns tHZCE 6 tEHQZ Chip Disable to Output Inactive 10 13 15 ns tLZOE 6 tGLQX Output Enable to Output Active 0 0 0 ns tHZOE 6 tGHQZ Output Disable to Output Inactive 10 13 15 ns tPU 3 tELICCH Chip Enable to Power Active 0 0 0 ns tPD 3 tEHICCL Chip Disable to Power Standby 25 35 45 ns Switching Waveforms Figure 5 SRAM Read Cycle 1 Address Controlled 4 5 Figure 6 SRAM Read Cycle 2 CE and OE Cont...

Page 8: ...ess Setup to Start of Write 0 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 0 ns tHZWE 6 7 tWLQZ Write Enable to Output Disable 10 13 15 ns tLZWE 6 tWHQX Output Active After End of Write 5 5 5 ns Switching Waveforms Figure 7 SRAM Write Cycle 1 WE Controlled 7 8 Figure 8 SRAM Write Cycle 2 CE and OE Controlled 7 8 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA...

Page 9: ...Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 6 V Switching Waveform Figure 9 AutoStore INHIBIT Power Up RECALL VCC VSWITCH VRESET POWER UP RECALL DQ DATA OUT STORE INHIBIT 5V tHRECALL POWER UP RECALL BROWN OUT STORE INHIBIT NO RECALL VCC DID NOT GO BELOW VRESET BROWN OUT STORE INHIBIT NO RECALL VCC DID NOT GO BELOW VRESET BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH Note 9 tHR...

Page 10: ... ns tHACE 10 tELAX Address Hold Time 20 20 20 ns tRECALL 10 RECALL Duration 20 20 20 μs Switching Waveform Figure 10 CE Controlled Software STORE RECALL Cycle 11 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 10 The software sequence is clocked on the falling edge of CE without involving OE double clocking abor...

Page 11: ...058 28 Pin SOIC 330 mil STK11C68 C35 001 51695 28 Pin CDIP 300 mil STK11C68 L35 001 51696 28 Pin LCC 350 mil STK11C68 SF35ITR 001 85058 28 Pin SOIC 330 mil Industrial STK11C68 SF35I 001 85058 28 Pin SOIC 330 mil STK11C68 C35I 001 51695 28 Pin CDIP 300 mil STK11C68 L35I 001 51696 28 Pin LCC 350 mil Part Numbering Nomenclature Packaging Option TR Tape and Reel Blank Tube Speed 25 25 ns 35 35 ns Pack...

Page 12: ... STK11C68 SF45ITR 001 85058 28 Pin SOIC 330 mil Industrial STK11C68 SF45I 001 85058 28 Pin SOIC 330 mil STK11C68 C45I 001 51695 28 Pin CDIP 300 mil STK11C68 L45I 001 51696 28 Pin LCC 350 mil All parts are Pb free The above table contains Final information Contact your local Cypress sales representative for availability of these parts Ordering Information continued Speed ns Ordering Code Package Di...

Page 13: ...STK11C68 Document Number 001 50638 Rev Page 13 of 16 Package Diagrams Figure 11 28 Pin 330 Mil SOIC 51 85058 51 85058 A Feedback ...

Page 14: ...STK11C68 Document Number 001 50638 Rev Page 14 of 16 Figure 12 28 Pin 300 Mil Side Braze DIL 001 51695 Package Diagrams continued 001 51695 Feedback ...

Page 15: ...Number 001 50638 Rev Page 15 of 16 Figure 13 28 Pad 350 Mil LCC 001 51696 Package Diagrams continued 1 ALL DIMENSION ARE IN INCHES AND MILLIMETERS MIN MAX 2 JEDEC 95 OUTLINE MO 041 3 PACKAGE WEIGHT TBD 001 51696 Feedback ...

Page 16: ...s specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNES...

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