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STK12C68

Document Number: 001-51027 Rev. **

Page 13 of 20

Hardware STORE Cycle

Parameter

Alt

Description

STK12C68

Unit

Min

Max

t

STORE

[9, 14]

t

HLHZ

STORE Cycle Duration

10

ms

t

DHSB

[14, 19]

t

RECOVER,

t

HHQX

Hardware STORE High to Inhibit Off

700

ns

t

PHSB

t

HLHX

Hardware STORE Pulse Width

15

ns

t

HLBL

Hardware STORE Low to STORE Busy

300

ns

Switching Waveform

Figure 13. Hardware STORE Cycle

Note

19. t

DHSB

is only applicable after t

STORE

is complete.

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Summary of Contents for Perform STK12C68

Page 1: ...iption The Cypress STK12C68 is a fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile...

Page 2: ...p OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS Ground Ground for the Device The device is connected to ground of the system VCC Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progr...

Page 3: ...ed Write Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tHZWE after WE goes LOW AutoStore Operation The STK12C68 stores data to nvSRAM using one of three storage operations 1 Hardware store activated by HSB 2 Software store activated by an address sequence 3 AutoStore on device power down ...

Page 4: ... unconnected Hardware RECALL Power Up During power up or after any low power condition VCC VRESET an internal RECALL request is latched When VCC once again exceeds the sense voltage of VSWITCH a RECALL cycle is automatically initiated and takes tHRECALL to complete If the STK12C68 is in a Write state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm re...

Page 5: ...low voltage condi tions When VCAP VSWITCH all externally initiated STORE operations and SRAM Writes are inhibited AutoStore can be completely disabled by tying VCC to ground and applying 5V to VCAP This is the AutoStore Inhibit mode in this mode STOREs are only initiated by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the STK1...

Page 6: ...nes and so on The Vcap value specified in this data sheet includes a minimum and a maximum value size The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers who want to use a larger Vcap value to make sure there is extra store charge should discuss their Vcap size se...

Page 7: ...pendent on output loading and cycle rate Values obtained without output loads 10 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Do Not Care VCC Max Average current for duration tSTORE 2 mA ISB1 5 VCC Standby Current Standby Cycling TTL Input Levels tRC 25 ns CE VIH tRC 35 ns CE VIH tRC 45 ns CE VIH 27 24 20 mA mA mA ISB2 5 VCC Standby Current CE VCC 0 2V All others VIN 0 2V or VCC ...

Page 8: ...d 6 Parameter Description Test Conditions 28 SOIC 28 PDIP 300 mil 28 PDIP 600 mil 28 CDIP 28 LCC Unit ΘJA Thermal Resis tance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 46 55 45 16 55 84 46 1 95 31 C W ΘJC Thermal Resis tance Junction to Case 27 95 31 62 25 74 5 01 9 01 C W Figure 6 AC Test Loads AC Test Conditions...

Page 9: ...Active 5 5 5 ns tHZCE 9 tEHQZ Chip Disable to Output Inactive 10 10 12 ns tLZOE 9 tGLQX Output Enable to Output Active 0 0 0 ns tHZOE 9 tGHQZ Output Disable to Output Inactive 10 10 12 ns tPU 6 tELICCH Chip Enable to Power Active 0 0 0 ns tPD 6 tEHICCL Chip Disable to Power Standby 25 35 45 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 7 8 Figure 8 SRAM Read Cycle 2 CE and O...

Page 10: ...rite 0 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 0 ns tHZWE 9 10 tWLQZ Write Enable to Output Disable 10 13 14 ns tLZWE 9 tWHQX Output Active After End of Write 5 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 11 12 Figure 10 SRAM Write Cycle 2 CE Controlled 11 12 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMP...

Page 11: ...Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 9 V tVCCRISE VCC Rise Time 150 μs tVSBL 11 Low Voltage Trigger VSWITCH to HSB Low 300 ns Switching Waveform Figure 11 AutoStore Power Up RECALL WE Notes 13 tHRECALL starts from the time VCC rises above VSWITCH 14 CE and OE low for output behavior 15 CE and OE low and WE high for output behavior 16 HSB is asserted low for 1us when VCAP drops through ...

Page 12: ...0 ns tHACE 17 tELAX Address Hold Time 20 20 20 ns tRECALL RECALL Duration 20 20 20 μs Switching Waveform Figure 12 CE Controlled Software STORE RECALL Cycle 18 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 17 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts...

Page 13: ... tSTORE 9 14 tHLHZ STORE Cycle Duration 10 ms tDHSB 14 19 tRECOVER tHHQX Hardware STORE High to Inhibit Off 700 ns tPHSB tHLHX Hardware STORE Pulse Width 15 ns tHLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveform Figure 13 Hardware STORE Cycle Note 19 tDHSB is only applicable after tSTORE is complete Feedback ...

Page 14: ...s Ordering Code Package Diagram Package Type Operating Range 25 STK12C68 SF25TR 001 85058 28 pin SOIC 330 mil Commercial STK12C68 SF25 001 85058 28 pin SOIC 330 mil STK12C68 PF25 001 85014 28 pin PDIP 300 mil STK12C68 WF25 001 85017 28 pin PDIP 600 mil STK12C68 SF25ITR 001 85058 28 pin SOIC 330 mil Industrial STK12C68 SF25I 001 85058 28 pin SOIC 330 mil STK12C68 PF25I 001 85014 28 pin PDIP 300 mil...

Page 15: ...STK12C68 SF45ITR 001 85058 28 pin SOIC 330 mil Industrial STK12C68 SF45I 001 85058 28 pin SOIC 330 mil STK12C68 PF45I 001 85014 28 pin PDIP 300 mil STK12C68 WF45I 001 85017 28 pin PDIP 600 mil STK12C68 C45I 001 51695 28 pin CDIP 300 mil STK12C68 L45I 001 51696 28 pin LCC 350 mil All parts are Pb free The above table contains Final information Contact your local Cypress sales representative for ava...

Page 16: ...STK12C68 Document Number 001 51027 Rev Page 16 of 20 Package Diagrams Figure 14 28 Pin 330 Mil SOIC 51 85058 Figure 15 28 Pin 300 Mil PDIP 51 85014 51 85058 A 51 85014 D Feedback ...

Page 17: ...STK12C68 Document Number 001 51027 Rev Page 17 of 20 Figure 16 28 Pin 600 Mil PDIP 51 85017 Package Diagrams continued 51 85017 B Feedback ...

Page 18: ...STK12C68 Document Number 001 51027 Rev Page 18 of 20 Figure 17 28 Pin 300 Mil Side Braze DIL 001 51695 Package Diagrams continued 001 51695 Feedback ...

Page 19: ...Number 001 51027 Rev Page 19 of 20 Figure 18 28 Pad 350 Mil LCC 001 51696 Package Diagrams continued 1 ALL DIMENSION ARE IN INCHES AND MILLIMETERS MIN MAX 2 JEDEC 95 OUTLINE MO 041 3 PACKAGE WEIGHT TBD 001 51696 Feedback ...

Page 20: ...it as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FI...

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