Cypress Semiconductor Perform CY7C1370D Manual Download Page 16 | Manualshive

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CY7C1370D
CY7C1372D

Document #: 38-05555 Rev. *F

Page 16 of 28

119-Ball BGA Boundary Scan Order

[13, 14]

Bit #

Ball ID

Bit #

Ball ID

Bit #

Ball ID

Bit #

Ball ID

1

H4

23

F6

45

G4

67

L1

2

T4

24

E7

46

A4

68

M2

3

T5

25

D7

47

G3

69

N1

4

T6

26

H7

48

C3

70

P1

5

R5

27

G6

49

B2

71

K1

6

L5

28

E6

50

B3

72

L2

7

R6

29

D6

51

A3

73

N2

8

U6

30

C7

52

C2

74

P2

9

R7

31

B7

53

A2

75

R3

10

T7

32

C6

54

B1

76

T1

11

P6

33

A6

55

C1

77

R1

12

N7

34

C5

56

D2

78

T2

13

M6

35

B5

57

E1

79

L3

14

L7

36

G5

58

F2

80

R2

15

K6

37

B6

59

G1

81

T3

16

P7

38

D4

60

H2

82

L4

17

N6

39

B4

61

D1

83

N4

18

L6

40

F4

62

E2

84

P4

19

K7

41

M4

63

G2

85

Internal

20

J5

42

A5

64

H1

21

H6

43

K4

65

J3

22

G7

44

E4

66

2K

Notes:

13. Balls which are NC (No Connect) are pre-set LOW.
14. Bit# 85 is pre-set HIGH.

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Summary of Contents for Perform CY7C1370D

Page 1: ... operations with data being trans ferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent Write Read transitions The CY7C1370D and CY7C1372D are pin compatible and functionally equivalent to ZBT devices All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output re...

Page 2: ... CE1 CE2 CE3 OE READ LOGIC DQs DQPa DQPb D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER1 S E N S E A M P S O U T P U T R E G I S T E R S E CLK CEN WRITE DRIVERS ZZ Sleep Control ...

Page 3: ...0 pin TQFP Pinout A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BWb BWa CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25...

Page 4: ...Z NC 288M A A A1 A0 VSS VDD NC CY7C1370D 512K x 36 DQPc DQb A NC 36M DQc DQb DQc DQc DQc DQb DQb DQa DQa DQa DQa DQPa DQd DQd DQd DQd BWd 119 Ball BGA Pinout BWb 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U NC 36M DQa VDDQ NC 576M NC 1G NC DQb DQb DQb DQb A A A A A VDDQ CE2 A NC VDDQ NC VDDQ VDDQ VDDQ NC NC NC 144M NC 72M A DQb DQb DQb DQb NC NC NC NC TMS VDD A A DQPb A A ADV LD A CE3 NC VDD A ...

Page 5: ...Qb VDD NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb A CE1 NC CE3 BWb CEN A CE2 NC DQb DQb MODE NC DQb DQb NC NC NC NC 36M NC 72M VDDQ NC BWa CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS VSS VSS NC VSS VSS VSS VSS VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ A A VDD V...

Page 6: ...s OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When asserted LOW the clock signal is recognized by the SRAM When deasserted HIGH the clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend th...

Page 7: ...als its output will tri state following the next clock rise Burst Read Accesses The CY7C1370D and CY7C1372D have an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequen...

Page 8: ...ove When ADV LD is driven HIGH on the subse quent clock rise the chip enables CE1 CE2 and CE3 and WE inputs are ignored and the burst counter is incremented The correct BW BWa b c d for CY7C1370D and BWa b for CY7C1372D inputs must be driven in each cycle of the burst write in order to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM...

Page 9: ...ed internally during write cycles During a read cycle DQs and DQPX Three state when OE is inactive or when the device is deselected and DQs data when OE is active Truth Table 1 2 3 4 5 6 7 Operation Address Used CE ZZ ADV LD WE BWx OE CEN CLK DQ Deselect Cycle None H L L X X X L L H Tri State Continue Deselect Cycle None X L H X X X L L H Tri State Read Cycle Begin Burst External L L L H X L L L H...

Page 10: ...es c b a L H L L L Write Byte d DQd and DQPd L L H H H Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L L L H H Write Bytes d c a L L L H L Write Bytes d c b L L L L H Write All Bytes L L L L L Function CY7C1372D WE BWb BWa Read H x x Write No Bytes Written L H H Write Byte a DQa and DQPa L H L Write Byte b DQb and DQPb L L H Write Both Bytes L L L ...

Page 11: ... unused in an application TDI is connected to the most signif icant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any r...

Page 12: ... be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places al...

Page 13: ...uctions are not implemented but are reserved for future use Do not use these instructions TAP Timing TAP AC Switching Characteristics Over the Operating Range 9 10 Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 ns tTF TCK Clock Frequency 20 MHz tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW ...

Page 14: ...1 All voltages referenced to VSS GND TDO 1 5V 20pF Z 50Ω O 50Ω TDO 1 25V 20pF Z 50Ω O 50Ω TAP DC Electrical Characteristics And Operating Conditions 0 C TA 70 C VDD 3 3V 0 165V unless otherwise noted 11 Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH 4 0 mA VDDQ 3 3V 2 4 V IOH 1 0 mA VDDQ 2 5V 2 0 V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 3 3V 2 9 V VDDQ 2 5V 2 1 V...

Page 15: ...laces the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do ...

Page 16: ... 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83 N4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 A5 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K Notes 13 Balls whi...

Page 17: ...8 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 ...

Page 18: ...I O 1 7 VDD 0 3V V VIL Input LOW Voltage 16 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply VDD Max IOUT 0 mA f fMAX 1 tCYC 4 ns cycle 250 MHz 350 m...

Page 19: ...onditions 100 TQFP Package 119 BGA Package 165 FBGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 28 66 23 8 20 7 C W ΘJC Thermal Resistance Junction to Case 4 08 6 2 4 0 C W OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z0 50Ω VT 1 5V 3 3V ALL INPUT PULSES VDD...

Page 20: ...Set up 1 2 1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 4 0 5 ns tDH Data Input Hold After CLK Rise 0 3 0 4 0 5 ns tCENH CEN Hold After CLK Rise 0 3 0 4 0 5 ns tWEH WE BWx Hold After CLK Rise 0 3 0 4 0 5 ns tALH ADV LD Hold after CLK Rise 0 3 0 4 0 5 ns tCEH Chip Select Hold After CLK Rise 0 3 0 4 0 5 ns Notes 19 This part has a voltage regulator internally tPower is the time power ...

Page 21: ... sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWx ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS Data In Out DQ tCLZ D A1 D A2 D A5 Q A4 Q A3 D A2 1 tDOH tCHZ tCO WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRIT...

Page 22: ...to deselect the device 30 I Os are in High Z when exiting ZZ sleep mode NOP STALL and DESELECT Cycles 25 26 28 ZZ Mode Timing 29 30 Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE WE CEN BWx ADV LD ADDRESS A3 A4 A5 D A4 Data In Out DQ A1 Q A5 WRITE D A4 STALL WRITE D A1 1 2 3 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A2 D A1 Q A2 Q A3 tZZ I SU...

Page 23: ...id Array 14 x 22 x 2 4 mm Lead Free CY7C1372D 167BGXI CY7C1370D 167BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1372D 167BZI CY7C1370D 167BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1372D 167BZXI 200 CY7C1370D 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1372D 200AXC CY7C1370D 200BGC 51 85115 119...

Page 24: ... Lead Free CY7C1372D 250BZXC CY7C1370D 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1372D 250AXI CY7C1370D 250BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1372D 250BGI CY7C1370D 250BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1372D 250BGXI CY7C1370D 250BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm C...

Page 25: ...IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31 50 51 80 81 GAUGE PLANE 1 00 REF 0 20 MIN SEATING PLANE 100 Pin Thin Plastic Quad...

Page 26: ... J U P N M T R 12 00 19 50 30 TYP 2 40 MAX A1 CORNER 0 70 REF U T R P N M L K J H G F E D C A B 2 1 4 3 6 5 7 Ø1 00 3X REF 7 62 22 00 0 20 14 00 0 20 1 27 0 60 0 10 C 0 15 C B A 0 15 4X Ø0 05 M C Ø0 75 0 15 119X Ø0 25 M C A B SEATING PLANE 0 90 0 05 3 81 10 16 0 25 C 0 56 51 85115 B 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 Feedback ...

Page 27: ...marks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Package Diagrams continued A 1 PIN 1 CORNER 15 00 0 10 13 00 0 10 7 00 1 00 Ø0 50 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H...

Page 28: ...r FBGA Package from 46 and 3 C W to 20 7 and 4 0 C W respectively Modified VOL VOH test conditions Removed shading from AC DC Table and Selection Guide Removed comment of Lead free BG packages availability below the Ordering Information Updated Ordering Information Table Changed from Preliminary to final D 370734 See ECN PCI Modified test condition in note 17 from VDDQ VDD to VDDQ VDD E 416321 See...

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