Cypress Semiconductor Perform CY7C132 Manual Download Page 10

Page: 10 / 15

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E

Page 10 of 15

Figure 10. Busy Timing Diagram No. 2 (Address Arbitration)

Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)

Switching Waveforms

(continued)

Left Address Valid First:

ADDRESS MATCH

ADDRESS

BUSY

ADDRESS MISMATCH

or t

BLA

BHA

ADDRESS

ADDRESS MATCH

ADDRESS MISMATCH

ADDRESS

BUSY

or t

BLA

BHA

ADDRESS

Right Address Valid First:

PWE

BUSY

R/W

[+] Feedback

Summary of Contents for Perform CY7C132

Page 1: ... conjunction with the CY7C142 CY7C146 SLAVE dual port device They are used in systems that require 16 bit or greater word widths This is the solution to applications that require shared or buffered data such as cache memory for DSP bit slice or multiprocessor designs Each port has independent control pins chip enable CE write enable R W and output enable OE BUSY flags are provided on each port In ...

Page 2: ... 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I O7R A1L A2L A3L A4L A5L A6L A7L A8L A9L I O0L I O1L I O2L I O3L I O I O I O I O I O I O I O I O I O I O I O 4L 5L 6L 7L 0R 1R 2R 3R 4R 5R 6R NC GND OE BUSY INT A R W CE R W BUSY INT 0L L L L L L CE R R R R 7C136 7C136A 7C146 A 10L A 10R 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37...

Page 3: ...36 25 30 7C142 30 7C146 25 30 7C132 35 45 7C136 35 45 7C142 35 45 7C146 35 45 7C132 55 7C136 55 7C136A 55 7C142 55 7C146 55 Unit Min Max Min Max Min Max Min Max VOH Output HIGH voltage VCC Min IOH 4 0 mA 2 4 2 4 2 4 2 4 V VOL Output LOW voltage IOL 4 0 mA 0 4 0 4 0 4 0 4 V IOL 16 0 mA 5 0 5 0 5 0 5 0 5 VIH Input HIGH voltage 2 2 2 2 2 2 2 2 V VIL Input LOW voltage 0 8 0 8 0 8 0 8 V IIX Input load ...

Page 4: ... Cycle Time 15 25 30 ns tAA Address to Data Valid 9 15 25 30 ns tOHA Data Hold from Address Change 0 0 0 ns tACE CE LOW to Data Valid 9 15 25 30 ns tDOE OE LOW to Data Valid 9 10 15 20 ns tLZOE OE LOW to Low Z 7 10 3 3 3 ns tHZOE OE HIGH to High Z 7 10 11 10 15 15 ns tLZCE CE LOW to Low Z 7 10 3 5 5 ns tHZCE CE HIGH to High Z 7 10 11 10 15 15 ns tPU CE LOW to Power Up 7 0 0 0 ns tPD CE HIGH to Pow...

Page 5: ...Time 15 25 25 ns tINS Address to INTERRUPT Set Time 15 25 25 ns tOINR OE to INTERRUPT Reset Time 13 15 25 25 ns tEINR CE to INTERRUPT Reset Time 13 15 25 25 ns tINR Address to INTERRUPT Reset Time 13 15 25 25 ns Shaded areas contain preliminary information Switching Characteristics Over the Operating Range Speeds 15 25 30 8 continued Parameter Description 7C136 15 4 7C146 15 7C132 25 4 7C136 25 7C...

Page 6: ...E HIGH to Power Down 7 35 35 35 ns Write Cycle 12 tWC Write Cycle Time 35 45 55 ns tSCE CE LOW to Write End 30 35 40 ns tAW Address Setup to Write End 30 35 40 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Setup to Write Start 0 0 0 ns tPWE R W Pulse Width 25 30 30 ns tSD Data Setup to Write End 15 20 20 ns tHD Data Hold from Write End 0 0 0 ns tHZWE R W LOW to High Z 7 20 20 25 ns tLZWE...

Page 7: ...Range Speeds 35 45 55 8 continued Parameter Description 7C132 35 7C136 35 7C142 35 7C146 35 7C132 45 7C136 45 7C142 45 7C146 45 7C132 55 7C136 55 7C136A 55 7C142 55 7C146 55 Unit Min Max Min Max Min Max Switching Waveforms Figure 4 Read Cycle No 1 Either Port Address Access 17 18 Figure 5 Read Cycle No 2 Either Port CE OE 17 19 tRC tAA tOHA DATA VALID PREVIOUS DATA VALID DATA OUT ADDRESS tACE tLZO...

Page 8: ...ed tBHA tBDD VALID tDDD tWDD ADDRESS MATCH ADDRESS MATCH R WR ADDRESSR DINR ADDRESSL BUSYL DOUTL tPS tBLA tRC tPWE VALID tAW tWC DATA VALID HIGH IMPEDANCE tSCE tSA tPWE tHD tSD tHA tHZOE CE R W ADDRESS OE DOUT DATAIN Note 20 If OE is LOW during a R W controlled write cycle the write pulse width must be the larger of tPWE or tHZWE tSD to allow the data I O pins to enter high impedance and for data ...

Page 9: ...ing Waveforms continued tAW tWC tSCE tSA tPWE tHD tSD tHZWE tHA HIGH IMPEDANCE CE R W ADDRESS DOUT DATAIN tLZWE DATA VALID ADDRESS MATCH tPS CEL Valid First tBLC tBHC ADDRESS MATCH tPS tBLC tBHC BUSYL CER CEL ADDRESSL R BUSYR CEL CER ADDRESSL R CER Valid First Note 21 If the CE LOW transition occurs simultaneously with or after the R W LOW transition the outputs remain in a high impedance state Fe...

Page 10: ... 11 Busy Timing Diagram No 3 Write with BUSY Slave CY7C142 CY7C146 Switching Waveforms continued Left Address Valid First ADDRESS MATCH tPS ADDRESSL BUSYR ADDRESS MISMATCH tRC or tWC tBLA tBHA ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL BUSYL tRC or tWC tBLA tBHA ADDRESSR Right Address Valid First tPWE tWB tWH BUSY R W CE Feedback ...

Page 11: ...Clears INTR Figure 14 Right Side Sets INTL Figure 15 Right Side Clears INTL Switching Waveforms continued WRITE 7FF tINS ADDRESSL R WL tWC tEINS CEL tHA tSA tWINS INTR READ 7FF tRC tEINR tHA tINR tOINR ADDRESSR CER R WR INTR OER WRITE 7FE tINS ADDRESSR R WR tWC tEINS CER tHA tSA tWINS INTL READ 7FE tEINR tHA tINR tOINR ADDRESSL CEL R WL INTL OEL tRC Feedback ...

Page 12: ...EMPERATURE AMBIENT TEMPERATURE C 1 4 1 3 1 2 1 0 0 9 4 0 4 5 5 0 5 5 6 0 NORMALIZED t AA SUPPLY VOLTAGE V NORMALIZED ACCESS TIME vs SUPPLY VOLTAGE 120 140 100 60 40 20 0 0 1 0 2 0 3 0 4 0 OUTPUT SINK CURRENT mA 0 80 OUTPUT VOLTAGE V OUTPUT SINK CURRENT vs OUTPUT VOLTAGE 0 6 0 8 1 25 1 0 0 75 10 40 NORMALIZED I CC 0 50 NORMALIZED ICC vs CYCLE TIME CYCLE FREQUENCY MHz 3 0 2 5 2 0 1 5 0 5 0 1 0 2 0 3...

Page 13: ...hip Carrier Pb Free CY7C136 55NC 51 85042 52 Pin Plastic Quad Flatpack CY7C136 55NXC 52 Pin Plastic Quad Flatpack Pb Free CY7C136 55JI 51 85004 52 Pin Plastic Leaded Chip Carrier Industrial CY7C136A 55JXI 52 Pin Plastic Leaded Chip Carrier Pb Free CY7C136 55NI 51 85042 52 Pin Plastic Quad Flatpack CY7C136A 55NXI 52 Pin Plastic Quad Flatpack Pb Free 15 CY7C146 15JC 51 85004 52 Pin Plastic Leaded Ch...

Page 14: ...136 CY7C136A CY7C142 CY7C146 Document 38 06031 Rev E Page 14 of 15 Package Diagrams Figure 17 52 Pin Plastic Leaded Chip Carrier 51 85004 Figure 18 52 Pin Plastic Quad Flatpack 51 85042 51 85004 A 51 85042 Feedback ...

Page 15: ...TED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems ...

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