CY62146E MoBL
®
4-Mbit (256K x 16) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-07970 Rev. *D
Revised February 01, 2008
Features
■
Very high speed: 45 ns
■
Wide voltage range: 4.5V–5.5V
■
Ultra low standby power
❐
Typical standby current: 1
μ
A
❐
Maximum standby current: 7
μ
A
■
Ultra low active power
❐
Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 44-pin TSOP II package
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life
™
(MoBL
®
) in portable appli-
cations such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (IO
0
through
IO
15
) are placed in a high impedance state when:
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. See
Table 1
for a complete description
of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines
.
256K x 16
RAM Array
IO
0
–IO
7
ROW DEC
O
DER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
CE
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
A
17
Logic Block Diagram
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