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CY7C1470V33
CY7C1472V33
CY7C1474V33

Document #: 38-05289 Rev. *I

Page 22 of 29

NOP, STALL and DESELECT Cycles

[22, 23, 25]

ZZ

Mode Timing

[26, 27]

Notes:

25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle.
26. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
27. I/Os are in High-Z when exiting ZZ sleep mode.

Switching Waveforms

(continued)

READ

Q(A3)

4

5

6

7

8

9

10

CLK

CE

WE

CEN

BWx

ADV/LD

ADDRESS

A3

A4

A5

D(A4)

Data

In-Out (DQ)

A1

Q(A5)

WRITE

D(A4)

STALL

WRITE

D(A1)

1

2

3

READ

Q(A2)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

t

CHZ

A2

D(A1)

Q(A2)

Q(A3)

t

ZZ

I

SUPPLY

CLK

ZZ

t

ZZREC

ALL INPUTS

(except ZZ)

DON’T CARE

I

DDZZ

t

ZZI

t

RZZI

Outputs (Q)

High-Z

DESELECT or READ Only

[+] Feedback

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Summary of Contents for NoBL CY7C1470V33

Page 1: ... required to enable consecutive Read Write operations with data being trans ferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent Write Read transitions The CY7C1470V33 CY7C1472V33 and CY7C1474V33 are pin compatible and functionally equiv alent to ZBT devices All synchronous inputs pass through input registers controlled by the risin...

Page 2: ...CY CONTROL LOGIC BWd BWe BWf BWg BWh Logic Block Diagram CY7C1474V33 1M x 72 A0 A1 A C MODE BWa BWb WE CE1 CE2 CE3 OE READ LOGIC DQs DQPa DQPb D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E IN...

Page 3: ...CY7C1470V33 100 pin TQFP Packages A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BWb BWa CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2...

Page 4: ...DD NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb A CE1 CE3 BWb CEN A CE2 NC DQb DQb MODE NC DQb DQb NC NC NC A VDDQ BWa CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS VSS VSS NC VSS VSS VSS VSS VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ A A VDD VSS VDD VSS VSS VDDQ VD...

Page 5: ...f NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe A A A A NC NC NC 144M A A NC 288M A A A A A A A1 A0 A A A A A A NC 576M NC NC NC NC NC BWSb BWSf BWSe BWSa BWSc BWSg BWSd BWSh TMS TDI TDO TCK NC NC MODE NC CEN VSS NC CLK NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS NC 1G VDD NC OE CE3 CE1 CE2 ADV LD WE VSS VSS VSS VSS VSS VSS VSS ZZ VSS VSS VSS VSS NC VDDQ VS...

Page 6: ...O pins When LOW the I O pins are allowed to behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When asserted LOW the clock signal is recognized by the ...

Page 7: ...vice is also pipelined Therefore when the SRAM is deselected at clock rise by one of the chip enable signals its output will tri state following the next clock rise Burst Read Accesses The CY7C1470V33 CY7C1472V33 and CY7C1474V33 have an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must b...

Page 8: ...s of the state of OE Burst Write Accesses The CY7C1470V33 CY7C1472V33 and CY7C1474V33 has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Write opera tions without reasserting the address inputs ADV LD must be driven LOW in order to load the initial address as described in the Single Write Access section above When ADV LD is driven HIGH o...

Page 9: ...t is masked internally during Write cycles During a Read cycle DQs and DQP a d tri state when OE is inactive or when the device is deselected and DQs data when OE is active Truth Table 1 2 3 4 5 6 7 Operation Address Used CE ZZ ADV LD WE BWx OE CEN CLK DQ Deselect Cycle None H L L X X X L L H Tri State Continue Deselect Cycle None X L H X X X L L H Tri State Read Cycle Begin Burst External L L L H...

Page 10: ... Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L L L H H Write Bytes d c a L L L H L Write Bytes d c b L L L L H Write All Bytes L L L L L Function CY7C1472V33 WE BWb BWa Read H x x Write No Bytes Written L H H Write Byte a DQa and DQPa L H L Write Byte b DQb and DQPb L L H Write Both Bytes L L L Function CY7C1474V33 WE BWx Read H x Write No Bytes ...

Page 11: ...The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller Stat...

Page 12: ... SAMPLE PRELOAD rather it performs a capture of the I O ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP contr...

Page 13: ...on a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing t TL Test Clock TCK 1 2 3 4 5 6 Test Mode Select TMS tTH Test Data Out TDO tCYC Test Data In TDI tTMSH tTMSS tTDIH tTDIS tTDOX tTDOV DON T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range 9 10 Parameter Description Min Max Unit Clock tTCYC TCK ...

Page 14: ... TDO 1 5V 20pF Z 50Ω O 50Ω TDO 1 25V 20pF Z 50Ω O 50Ω TAP DC Electrical Characteristics And Operating Conditions 0 C TA 70 C VDD 3 135V to 3 6V unless otherwise noted 11 Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH 4 0 mA VDDQ 3 3V 2 4 V IOH 1 0 mA VDDQ 2 5V 2 0 V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 3 3V 2 9 V VDDQ 2 5V 2 1 V VOL1 Output LOW Voltage IOL 8 0 ...

Page 15: ...71 52 Boundary Scan Order 209 FBGA 110 Identification Codes Instruction Code Description EXTEST 000 Captures I O ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM o...

Page 16: ... 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 ...

Page 17: ...1 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E...

Page 18: ...O 1 7 VDD 0 3V V VIL Input LOW Voltage 13 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply VDD Max IOUT 0 mA f fMAX 1 tCYC 4 0 ns cycle 250 MHz 500 m...

Page 19: ... 209 FBGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 24 63 16 3 15 2 C W ΘJC Thermal Resistance Junction to Case 2 28 2 1 1 7 C W AC Test Loads and Waveforms Note 15 Tested initially and after any design or process changes that may affect these parameters OUTPUT R 317Ω R 351Ω 5 p...

Page 20: ...ip Select Set up 1 4 1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 4 0 4 0 5 ns tDH Data Input Hold After CLK Rise 0 4 0 4 0 5 ns tCENH CEN Hold After CLK Rise 0 4 0 4 0 5 ns tWEH WE BWx Hold After CLK Rise 0 4 0 4 0 5 ns tALH ADV LD Hold after CLK Rise 0 4 0 4 0 5 ns tCEH Chip Select Hold After CLK Rise 0 4 0 4 0 5 ns Notes 16 Timing reference is 1 5V when VDDQ 3 3V and is 1 25V when VD...

Page 21: ...he Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWx ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS Data In Out DQ tCLZ D A1 D A2 D A5 Q A4 Q A3 D A2 1 tDOH tCHZ tCO WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q...

Page 22: ...mode See cycle description table for all possible signal conditions to deselect the device 27 I Os are in High Z when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE WE CEN BWx ADV LD ADDRESS A3 A4 A5 D A4 Data In Out DQ A1 Q A5 WRITE D A4 STALL WRITE D A1 1 2 3 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A2 D A1 Q A2 Q A3 ...

Page 23: ...C1470V33 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm Lead Free CY7C1472V33 167BZXI CY7C1474V33 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1474V33 167BGXI 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm Lead Free 200 CY7C1470V33 200AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1472V33 200AXC CY7C1470V33 200BZ...

Page 24: ...7C1470V33 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1472V33 250AXI CY7C1470V33 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472V33 250BZI CY7C1470V33 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1472V33 250BZXI CY7C1474V33 250BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm...

Page 25: ...ENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31 50 51 80 81 GAUGE PLANE 1 00 REF 0 20 MIN SEATING PLANE 100 Pin Thin Plas...

Page 26: ... 1 00 Ø0 45 0 05 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A C 1 00 5 00 0 36 0 05 0 10 165 ball FBGA 15 x 17 x 1 4 mm 51 85165 51 85165 A Feedback ...

Page 27: ... express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemn...

Page 28: ...e offering C 235012 See ECN RYQ Minor Change The data sheets do not match on the spec system and external web D 243572 See ECN NJY Changed ball C11 D11 E11 F11 G11 from DQPb DQb DQb DQb DQb to DQPa DQa DQa DQa DQa in page 4 Modified capacitance values in page 20 E 299511 See ECN SYT VBL Removed 225 MHz offering and included 250 MHz speed bin Changed tCYC from 4 4 ns to 4 0 ns for 250 MHz Speed Bin...

Page 29: ... 30 µA Changed VDDQ VDD to VDDQ VDD in page 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table I 472335 See ECN VKN Corrected the typo in the pin configuration for 209 Ball FBGA pinout Corrected the ball name for H9 to VSS from VSSQ Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH tTL from 25 ...

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