Cypress Semiconductor NoBL CY7C1470BV33 Specification Sheet Download Page 21

Page: 21 / 30

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C

Page 21 of 30

SB3

Automatic CE
Power Down
Current—CMOS Inputs

Max. V

, Device Deselected,

≤

0.3V or V

> V

DDQ

−

0.3V,

f = f

MAX

= 1/t

CYC

4.0-ns cycle, 250 MHz

245

5.0-ns cycle, 200 MHz

245

6.0-ns cycle, 167 MHz

245

SB4

Automatic CE
Power Down
Current—TTL Inputs

Max. V

, Device Deselected,

≥

or V

≤

, f = 0

All speed grades

135

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter

Description

Test Conditions

100 TQFP

Max

165 FBGA

Max

209 FBGA

Max

Unit

ADDRESS

Address Input Capacitance

= 25

C, f = 1 MHz,

= 3.3V

DDQ

= 2.5V

DATA

Data Input Capacitance

CTRL

Control Input Capacitance

CLK

Clock Input Capacitance

Input/Output Capacitance

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameters

Description

Test Conditions

100 TQFP

Package

165 FBGA

Package

209 FBGA

Package

Unit

Thermal Resistance
(Junction to Ambient)

Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.

24.63

16.3

15.2

C/W

Thermal Resistance
(Junction to Case)

2.28

2.1

1.7

C/W

AC Test Loads and Waveforms

Electrical Characteristics

Over the Operating Range

[13, 14]

(continued)

Parameter

Description

Test Conditions

Min

Max

Unit

OUTPUT

R = 317

R = 351

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

= 50

= 1.5V

3.3V

ALL INPUT PULSES

DDQ

GND

90%

10%

90%

10%

≤

1 ns

≤

1 ns

(c)

3.3V IO Test Load

OUTPUT

R = 1667

R = 1538

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

= 50

= 1.25V

2.5V

ALL INPUT PULSES

DDQ

GND

90%

10%

90%

10%

≤

1 ns

≤

1 ns

(c)

2.5V IO Test Load

[+] Feedback

Summary of Contents for NoBL CY7C1470BV33

Page 1: ...imited true back to back read or write operations with no wait states The CY7C1470BV33 CY7C1472BV33 and CY7C1474BV33 are equipped with the advanced NoBL logic required to enable consecutive read or write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent read or write transitions The CY7C1470BV33 CY...

Page 2: ...Y CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S E N S E A M P S E CLK CEN WRITE DRIVERS BW c BW d ZZ SLEEP CONTROL O U T P U T R E G I S T E R S A0 A1 A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQPa DQPb D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGI...

Page 3: ...T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S E N S E A M P S O U T P U T R E G I S T E R S E CLK CEN WRITE DRIVERS BW a BW b WE ZZ Sleep Control BW c WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW d BW e BW f BW g BW h ...

Page 4: ...7C1470BV33 A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BWb BWa CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 ...

Page 5: ...C VSS VDDQ NC DQPb VDDQ VDD DQb DQb DQb NC DQb NC DQa DQa VDD VDDQ VDD VDDQ DQb VDD NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb A CE1 CE3 BWb CEN A CE2 NC DQb DQb MODE NC DQb DQb NC NC NC A VDDQ BWa CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS VSS VSS ...

Page 6: ...DQPf DQa DQa DQa DQa DQe DQe DQe DQe DQPa DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe A A A A NC NC NC 144M A A NC 288M A A A A A A A1 A0 A A A A A A NC 576M NC NC NC NC NC BWSb BWSf BWSe BWSa BWSc BWSg BWSd BWSh TMS TDI TDO TCK NC NC MODE NC CEN VSS NC CLK NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS NC 1G VDD NC OE CE3 CE1 CE2 ADV LD...

Page 7: ...n of the IO pins When LOW the IO pins are enabled to behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Synchronous Clock Enable Input Active LOW When asserted LOW the clock signal is recognized...

Page 8: ...rite or deselect can be initiated Deselecting the device is also pipelined Therefore when the SRAM is deselected at clock rise by one of the chip enable signals its output tri states following the next clock rise Burst Read Accesses The CY7C1470BV33 CY7C1472BV33 and CY7C1474BV33 have an on chip burst counter that enables the user to supply a single address and conduct up to four reads without reas...

Page 9: ...ally tri stated during the data portion of a write cycle regardless of the state of OE Burst Write Accesses The CY7C1470BV33 CY7C1472BV33 and CY7C1474BV33 has an on chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs ADV LD must be driven LOW to load the initial address as described in Single Write Acces...

Page 10: ...Next X L H X H X L L H Tri State Ignore Clock Edge Stall Current X L X X X X H L H Sleep Mode None X H X X X X X X Tri State Notes 1 X Don t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BWx 0 signifies at least one Byte Write Select is active BWx Valid signifies that the desired byte write selects are asserted see Partial Write Cycle Description on page 11 for details 2 Writ...

Page 11: ...ytes c b a L H L L L Write Byte d DQd and DQPd L L H H H Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L L L H H Write Bytes d c a L L L H L Write Bytes d c b L L L L H Write All Bytes L L L L L Function CY7C1472BV33 WE BWb BWa Read H x x Write No Bytes Written L H H Write Byte a DQa and DQPa L H L Write Byte b DQb and DQPb L L H Write Both Bytes L...

Page 12: ... resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram TDI is internally p...

Page 13: ...ST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the IO ring when these instruc tions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instructi...

Page 14: ...rming a SAMPLE PRELOAD instruction has the same effect as the Pause DR command BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Reserve...

Page 15: ...Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns Setup Times tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Notes 9 tCS and tCH refer to the setup and hold time requirements of latching ...

Page 16: ... TAP AC Output Load Equivalent TDO 1 25V 20pF Z 50Ω O 50Ω TAP DC Electrical Characteristics And Operating Conditions 0 C TA 70 C VDD 3 135V to 3 6V unless otherwise noted 11 Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH 4 0 mA VDDQ 3 3V 2 4 V IOH 1 0 mA VDDQ 2 5V 2 0 V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 3 3V 2 9 V VDDQ 2 5V 2 1 V VOL1 Output LOW Voltage IOL ...

Page 17: ...165 FBGA 71 52 Boundary Scan Order 209 FBGA 110 Table 8 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does n...

Page 18: ...1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Table 10 Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5...

Page 19: ... 91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79...

Page 20: ... Voltage For 3 3V IO IOL 8 0 mA 0 4 V For 2 5V IO IOL 1 0 mA 0 4 V VIH Input HIGH Voltage 13 For 3 3V IO 2 0 VDD 0 3V V For 2 5V IO 1 7 VDD 0 3V V VIL Input LOW Voltage 13 For 3 3V IO 0 3 0 8 V For 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 μA Input Current of MODE Input VSS 30 μA Input VDD 5 μA Input Current of ZZ Input VSS 5 μA Input VDD 30 μA IOZ Output Leakag...

Page 21: ...apacitance 6 6 6 pF CIO Input Output Capacitance 5 5 5 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters Parameters Description Test Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per...

Page 22: ... Setup Before CLK Rise 1 4 1 4 1 5 ns tWES WE BWx Setup Before CLK Rise 1 4 1 4 1 5 ns tALS ADV LD Setup Before CLK Rise 1 4 1 4 1 5 ns tCES Chip Select Setup 1 4 1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 4 0 4 0 5 ns tDH Data Input Hold After CLK Rise 0 4 0 4 0 5 ns tCENH CEN Hold After CLK Rise 0 4 0 4 0 5 ns tWEH WE BWx Hold After CLK Rise 0 4 0 4 0 5 ns tALH ADV LD Hold after CLK...

Page 23: ...Data In Out DQ tCLZ D A1 D A2 D A5 Q A4 Q A3 D A2 1 tDOH tCHZ tCO WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 DESELECT OE tOEV tOELZ tOEHZ tDOH DON T CARE UNDEFINED Q A6 Q A4 1 Notes 20 For this waveform ZZ is tied LOW 21 When CE is LOW CE1 is LOW CE2 is HIGH and CE3 is LOW When CE is HIGH CE1 is HIGH CE2 is LOW or CE3 is HIGH 22 Order of the...

Page 24: ... A4 STALL WRITE D A1 1 2 3 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A2 D A1 Q A2 Q A3 t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI t RZZI Outputs Q High Z DESELECT or READ Only Notes 23 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrated CEN being used to create a pause A Write is not performed during this cycle 24 Device ...

Page 25: ...7C1470BV33 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb free CY7C1472BV33 167BZXI CY7C1474BV33 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1474BV33 167BGXI 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm Pb free 200 CY7C1470BV33 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb free Commercial CY7C1472BV33 200AXC CY7C1470BV33 20...

Page 26: ...CY7C1470BV33 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb free Industrial CY7C1472BV33 250AXI CY7C1470BV33 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472BV33 250BZI CY7C1470BV33 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb free CY7C1472BV33 250BZXI CY7C1474BV33 250BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 ...

Page 27: ...RUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 0 5 1 3 51...

Page 28: ...ed A 1 PIN 1 CORNER 17 00 0 10 15 00 0 10 7 00 1 00 Ø0 45 0 05 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A C 1 00 5 00 0 36 0 05 0 10 51 85165 A Feedback ...

Page 29: ...CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 Document 001 15031 Rev C Page 29 of 30 Figure 10 209 Ball FBGA 14 x 22 x 1 76 mm 51 85167 Package Diagrams continued 51 85167 Feedback ...

Page 30: ...rivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is pr...

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