Cypress Semiconductor NoBL CY7C1352G Specification Sheet Download Page 9

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CY7C1352G

Document #: 38-05514 Rev. *D

Page 9 of 12

Switching Waveforms

Read/Write Timing

[18, 19, 20]

Notes:

18. For this waveform ZZ is tied low.
19. When CE is LOW: CE

is LOW, CE

is HIGH and CE

is LOW. When CE is HIGH: CE

is HIGH or CE

is LOW or CE

is HIGH.

20. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.

WRITE

D(A1)

CLK

t CYC

CEH

CES

CEN

CENH

CENS

[A:B]

ADV/LD

ADDRESS

Data

In-Out (DQ)

CLZ

D(A1)

D(A2)

D(A5)

Q(A4)

Q(A3)

D(A2+1)

DOH

CHZ

WRITE

D(A2)

BURST
WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OEV

OELZ

OEHZ

DOH

DON’T CARE

UNDEFINED

Q(A6)

Q(A4+1)

[+] Feedback

Summary of Contents for NoBL CY7C1352G

Page 1: ...t Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximum access delay from the clock rise is 2 6 ns 2...

Page 2: ...A DQA NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 6...

Page 3: ...quence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When asserted LOW the Clock signal is recognized by the SRAM When deasserted HIGH the Clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required ZZ Input Asynchronous ZZ ...

Page 4: ...ap around when incremented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock ris...

Page 5: ... Begin Burst External L L L L L X L L H Data In D Write Cycle Continue Burst Next X L H X L X L L H Data In D NOP WRITE ABORT Begin Burst None L L L L H X L L H Tri State WRITE ABORT Continue Burst Next X L H X H X L L H Tri State IGNORE CLOCK EDGE Stall Current X L X X X X H L H SNOOZE MODE None X H X X X X X X Tri State Truth Table for Read Write 2 3 Function WE BWB BWA Read H X X Write No bytes...

Page 6: ... I O 1 7 VDD 0 3V V VIL Input LOW Voltage 9 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT 0 mA f fMAX 1 tCYC 4 ns cycle 250 M...

Page 7: ...andard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W ΘJC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 11 Tested initially and after any design or process changes that may affect these parameters Electrical Characteristics Over the Operating Range 9 10 continued Parameter Description Test Conditions Min Max Unit 1ns OUTPUT R 31...

Page 8: ...5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tALH ADV LD Hold after CLK Rise 0 3 0 5 0 5 0 5 ns tWEH GW BW A B Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tCENH CEN Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 3 0 5 0 5 0 5 ns Notes 12 This part has a voltage regulator internally tpower is the t...

Page 9: ...nce is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK tCYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BW A B ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS Data In Out DQ tCLZ D A1 D A2 D A5 Q A4 Q A3 D A2 1 tDOH tCHZ tCO WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D ...

Page 10: ...ode See cycle description table for all possible signal conditions to deselect the device 23 DQs are in high Z when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE WE CEN BW A B ADV LD ADDRESS A3 A4 A5 D A4 Data In Out DQ A1 Q A5 WRITE D A4 STALL WRITE D A1 1 2 3 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A2 D A1 Q A2 Q A3...

Page 11: ... Package Type Operating Range 133 CY7C1352G 133AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1352G 133AXI Industrial 166 CY7C1352G 166AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1352G 166AXI Industrial 200 CY7C1352G 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1352G 200AXI Industria...

Page 12: ...n the Thermal Resis tance table Added lead free product information for 119 BGA Updated the Ordering Information by shading and unshading MPNs as per avail ability C 419256 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Modified test condition from VIH VDD to VIH VDD Modified test con...

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