Cypress Semiconductor enCoRe CY7C604XX, Specification Sheet, Page: 10 / 30

CY7C604XX
Document Number: 001-12395 Rev *H Page 10 of 30
18 Power Vss Supply ground
19 NC NC No connection
20 NC NC No connection
21 Power Vdd Supply voltage
22 IOHR P1[0]
(3, 4)
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
23 IOHR P1[2] Digital I/O
24 IOHR P1[4] Digital I/O, optional external clock input (EXTCLK)
25 IOHR P1[6] Digital I/O
26 XRES Ext Reset Active high external reset with internal pull down
27 I/O P3[0] Digital I/O
28 I/O P3[2] Digital I/O
29 I/O P3[4] Digital I/O
30 I/O P3[6] Digital I/O
31 I/O P4[0] Digital I/O
32 I/O P4[2] Digital I/O
33 I/O P2[0] Digital I/O
34 I/O P2[2] Digital I/O
35 I/O P2[4] Digital I/O
36 I/O P2[6] Digital I/O
37 IOH P0[0] Digital I/O
38 IOH P0[2] Digital I/O
39 IOH P0[4] Digital I/O
40 IOH P0[6] Digital I/O
41 Power Vdd Supply voltage
42 NC NC No connection
43 NC NC No connection
44 IOH P0[7] Digital I/O
45 IOH P0[5] Digital I/O
46 IOH P0[3] Digital I/O
47 Power Vss Supply ground
48 IOH P0[1] Digital I/O
CP Power Vss Center pad must be connected to ground
LEGEND
I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Table 3. 48-Pin Part Pinout (QFN) (continued)
Pin No. Type Name Description
[+] Feedback