CYS25G0101DX-ATC Evaluation Board User’s Guide
4
1. Introduction
Cypress's CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high-speed SONET data communica-
tions. It provides complete parallel-to-serial and serial-to-parallel conversions, clock generation, and clock and data recovery opera-
tions in a single chip, optimized for full SONET/SDH compliance. The CYS25G0101DX Evaluation Board is designed for evaluating as
well as understanding the characteristics of the CYS25G0101DX SONET/SDH Transceiver. The CYS25G0101DX SONET/SDH
Transceiver Evaluation Board provides the following advantages.
2. Features
• Flexible and easy to operate
• On-board Cypress 120-pin TQFP CYS25G0101DX SONET/SDH Transceiver
• Supports LVPECL and HSTL interfaces
• Dip switch for selecting different diagnostic modes
• Four diagnostic modes – Diagnostic Loopback mode, Line Loopback mode, Analog Line Loopback mode, and factory TEST0
(Parallel Line Loopback) mode
• LFI and FIFO_ERR LEDs
• Onboard oscillator for the REFCLK
• Supports external clock source for the REFCLK
• 16-bit RxD, 16-bit TxD bus, RXCLK, TXCLKI, TXCLKO interface
• SMA connectors for CML input and output buffers
• Separate Banana Jacks for all voltage sources for measuring current individually
3. Kit Contents
• CYS25G0101DX Evaluation Board
• Certificate of Compliance
• CYS25G0101DX Evaluation Kit CD
—
Users Guide
—
Application Notes
—
Data Sheet
4. Functional Description
This board can be used to test the CYS25G0101DX in various modes, such as TEST0 (parallel line loopback mode), LINELOOP,
LOOPA and LOOPTIME. The REFCLK of the CYS25G0101DX is connected to the onboard 155.52-MHz oscillator. The on-board
REFCLK can be replaced by connecting the external reference clock source to J17 and J18. To use the external reference clock
source, the C400 and C401 (0.01-
µ
F cap) have to be removed and placed on C402 and C403 positions. Also, the P2, CLKVCC, has to
be disconnected from the power supply (or power down). The CYS25G0101DX Evaluation Board provides an optional optical module
interface for connecting to an optical module daughter card.
The block diagram of the CYS25G0101DX is shown in
Figure 1
. The detailed functional description can be found in the
CYS25G0101DX data sheet.
Figure 2
shows the picture of the CYS25G0101DX Evaluation Board and the location of the jumpers.
Table 1
is the description of all jumpers and connectors. The bus connectors, J1 and J2, are used to connect to the 16-bit RxD and TxD
buses for transferring and receiving the parallel data.
Table 2
and
Table 3
are the pin definitions of J1 and J2. A multi-function eight-po-
sition Dip switch provides the selection of the different diagnostic modes as well as the control functions.
Table 4
is the functional de-
scription of the Dip switch SW1. The TEST0 jumper, J6, when closed, is used to enable the factory TEST0 (Parallel Line Loop Back)
mode. In the “Parallel Line Loop Back” mode, parallel output buffers are internally jumped to the parallel input buffers. There is no need
to use external jumpers for the headers. J13, J14, J15, J16 and J4 are Differential CML input and output and power supply for the option-
al optical module daughter card.
Table 5
idescribes the optical module interface and
Table 6
idescribes the LED.
Figure 3
shows the
jumper orientations of the CYS25G0101DX Evaluation Board.
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